Lithography represents the greatest challenge to the continuation of Moore’s Law in its history. Even EUV won’t solve all problems.
By Brian Bailey
The end of Moore’s Law has been predicted for almost as long as the law has existed. It normally comes down to some great technological barrier that cannot be breached, only to find that a solution is just around the corner and the concerns fade until the next barrier is identified.
At DAC this year (2013), there were many predictions about why Moore’s Law will end in the near future including power issues, physical limits and semiconductor equipment and manufacturing cost. But there is another issue that has been pressing for quite a while and, so far, the industry has come up with workarounds to stop it becoming a problem. Still, the pressure is mounting and the lack of a solution is intensifying many other problems, namely the continued delays in extreme ultraviolet (EUV) lithography.
Lithography shrinking is the primary driver for device scaling, which in turn brings about voltage reduction, power reduction, smaller parasitics and lower cost. The shorter the wavelength of light that is used, the higher the possible resolution in the lithographic process. The industry has migrated from 365nm to 248nm and currently is using 193nm, but this already is 10 times the size of the lines being drawn. With 20nm process technology, the industry is being forced to move to double patterning in order to get the necessary resolution.
Double patterning adds complexity and increases production time, which in turn reduces the cost advantages of the newer nodes. For finer geometries, EDA companies already are talking about the need to go to even more mask sets. The answer that the industry has been looking for is the migration to EUV, which has a wavelength of 13.5nm, but EUV is a tough technology nut to crack.
In a recent article entitled “Litho Roadmap Remains Cloudy,” Mark LaPedus outlined the conflicts going on in the major fabrication houses regarding their next-generation lithography system and coupling that with the other impending change of migrating to 450mm wafers. He also talked about the problems associated with mask defects for EUV. This article focuses on some of the technical problems and their solutions and looking at the cost impact of these changes.
The state of EUV
Let’s starts with the biggies. First, EUV is absorbed by glass, meaning that traditional lens technology cannot be used. Instead, the beam has to be focused with mirrors, with each mirror absorbing about 30% of the light. In a typical system there are 10 mirrors, meaning that only a tiny fraction of the original power makes it to the mask. The second biggie is that EUV is absorbed by the air, meaning that is has to be created and used within a vacuum. These problems have been overcome to the extent that there is equipment being used in test fabs.
But there is a final problem that has to be overcome before the technology can move into production—power. Today (Feb 2013), the highest power laser being offered by Cymer, one of the leaders in this technology is in the 40W range, but it is estimated that 200W lasers will be necessary for full production. A 40W laser can process about 30 wafers an hour. With lower power, longer exposure times are needed, meaning that production volumes are lower and costs increase. In order to produce 200W of EUV it will require a laser in the order of 43kW. Translate that into the power it it demands from the socket, and it’s in the range of 0.5 megawatts.
So what is the workaround being used today? It comes in two parts. The first part is increasing the resolution from the existing process, which is controlled by two factors, the wavelength of the light and the aperture. We already mentioned the progress on the wavelength, currently at 193nm. The aperture controls the amount of light passing through the lens. Rayleigh’s resolution criterion says that resolution is proportional to the wavelength divided by the aperture, so if the wavelength cannot be manipulated in the near term, the apertures must grow, but this increases the cost of the equipment. This approach seemed like a dead end a few years ago when the numerical aperture hit the refractive index of air. The hurdle was crossed by switching to water-immersion lithography that has a refractive index greater than 1.0.
But that can only be pushed so far. The EDA industry has since been providing another level of workaround, namely double patterning (DP), which is being utilized at 20nm.
To understand the concept we need to delve into the physics a little more. First, it is important to understand that most chips are built using a regular array of devices, packed together as close as possible. This creates repeating patterns on the surface of the chip. The problems do not exist to the same degree when we are talking about single isolated lines. With 193nm wavelength and a numerical aperture of 1.35, the smallest repeating pattern possible is around 72nm or 36nm for half pitch. This gives us the minimum distance (center to center) between two lines and thus between two devices. Anything closer than this will not be seen by the exposure. If we were to use two masks, with each one having only half of the number of lines on it, we can print lines twice as close together. Of course, having to perform a double exposure increases the fabrication time and thus the cost.
There are various techniques used for double patterning, but the one in common usage is litho-etch-litho-etch (LELE). As the name suggests this is a litho-etch processes followed by a second litho-etch process. According to Tom Ferry, senior director of marketing for the Silicon Engineering Group at Synopsys, we probably will have to go to triple patterning or self-aligned double patterning by the time we get to 10nm. Mentor’s Gene Forte, Technology communications manager, adds “Right now, the leading strategy for the 10nm node appears to be layer-dependent multi-patterning, that is, a combination of triple patterning, double patterning and spacer assisted double patterning (SADP). DP will employ pitch splitting or gratings plus cut masks to define line ends and 2D shapes.”
Neal Carney, vice president of marketing and business development at Tela Innovations, says work is underway on an alternative method based on lines and cuts. With this they “have demonstrated wafer results down to 16nm with simple line patterns and single exposure cuts. Scaling to 10nm, two cut exposures were needed.” He postulates that it is possible that EUV could be used for the cuts while the lines would continue using the existing methods.
What approach—or combination of approaches—ultimately wins out is anyone’s guess. Aki Fujimura, CEO of D2S says, “Overlay accuracy demands increase in multiple patterning. Even though the features being printed are the same size (because they are already at the limit) as more and more masks are used, the accuracy demand on each mask’s impact on the wafer will continue to increase. Though many believe that mask complexity will not need to increase beyond the 14nm node, I believe that this increased demand on accuracy will require even more complex OPC or ideal ILT shapes to be written on the masks.”
In the table below, the relative costs for each method can be seen, although this has not been updated for a couple of years so there could have been some progress made since then.
An interesting question is what happens to the EDA flow when EUV does become available. Does the need for double patterning go away? Do design rules checks become simpler?
Synopsys’ Tom Ferry believes that while some things will get simpler, the need for double patterning may not go away, or if it does only for a short period of time. George Bailey, technical marketing director at Synopsys, added that at 10nm and using EUV we may be able to use single exposure, but by 7nm we would be back to double patterning. This is based on the wavelength/aperture problem because the aperture for EUV is going to be smaller (0.35) so even though we have an order of magnitude improvement on wavelength with EUV, we do not get an order of magnitude improvement in resolution. Gene Forte say “The k1 factor at the 10nm node with EUV @ NA=0.33 is around 0.5. The k1 factor can be thought of as a “process difficulty metric”, and double patterning typically becomes necessary below k1 ~ 0.28.”
But even though we may get some relief in design rule complexity, there will be some additional things to worry about, such as flare. This is a complete chip issue meaning that tools will have to work on a flattened database rather than dealing with small chunks at a time.
The consensus appears to be that there may some uptake of EUV at 10nm, but it will only be used for the most critical layers. Most layers will continue to use one of the current patterning techniques and with all alternatives the costs will increase from where we are today.
The following was added to the article after its initial publication.
Manoj Chacko, Product Marketing Director, DFM Silicon and Verification, Digital & Signoff Group, Cadence added another dimension to this story. In an email he stated that the cost of an EUV machine and its prohibitive throughput are probably more expensive than a fab floor with cheaper 193i scanners and a three mask solution. He continued saying that since lithography equipment cannot provide the needed resolution on the manufacturing side, DFM has become a necessary step. “We’ve seen DFM creep up the design chain and now most foundries have mandatory DFM checks. When EUV is introduced, there will still be a need for OPC compliance checks, litho checks, and DPT checks that need to be performed on designs prior to manufacturing, before tapeout and during design. DFM also includes mandatory CMP analysis to identify thickness variations in the interconnect stack. With FinFET technologies, we see the importance of CMP growing to predict and control the 3D front end structures. CMP issues can impact lithography depth-of-focus, create some cooper pooling (short) or other catastrophic variation. Model-based CMP can predict the long-range effect of CMP and the cumulative of thickness variation across the different layers of the stack.”
Conferences related to EUV lithography
International Workshop on EUV and Soft X-ray sources
SPIE Advanced Lithography