FinFET scaling faces challenges from parasitic resistance and capacitance.
As the industry moves beyond 10nm to the 7nm and 5nm nodes, fundamental shifts are needed to address scaling challenges. Among the priority concerns driving industry changes, particularly with respect to materials and architecture, is the impact on transistor performance from rising parasitic resistance and parasitic capacitance or RC. I spoke about this industry dilemma recently at the SEMICON West trade show.
Transistor gate lengths have shrunk a thousand-fold over the past 40 years. Various techniques have been used to support continuous CMOS scaling including fixed voltage scaling, oxide scaling and the introduction of strain engineering/HKMG materials to the architectural revolution of 3D finFET-body width scaling.
The finFET transistor structure sustained the chip industry by rescuing it from the short-channel effects that limited the device scalability of conventional planar transistors. But this same issue and the alarming rise in parasitic RC is signifying that the finFET is also reaching it limits.
FinFETs scale by getting taller and narrower. Taller, more rectangular fins help improve drive current and narrower fins enable faster switching and gate length scaling. However, as devices shrink node to node, up to 30% of contact width per node is lost, driving up resistance.
So, is the end near for finFETs? Several process and design modifications enable finFET scaling to 7nm, delivering the increased performance the industry demands. Contact resistance can be reduced by changing the barrier height and attaining precise dopant control. Further RC reduction can be achieved by changing the implant and anneal sequence to leverage amorphization and recrystallization of the contact interface to increase dopant activation. Wrap-around contact architectures can enable a 2x increase of the contact area. Plasma implant enables conformal S/D doping and drives RC numbers to a record low, 1.2e-9 and delivers more conformal coverage as the industry leverages area-enhanced contact areas with challenging feature aspect ratios.
But finFET scalability beyond 7nm is extremely challenging, as fin widths needed for gate length (Lg) scaling increase threshold voltage (Vt) variability. At 5nm, it appears that silicon and the finFET structure will not be thick enough to prevent quantum tunneling and gate leakage.
What are obviously required are new materials and new architectures. New materials being explored include using Co for the contact as well as lower-k spacers and integration solutions, such as air-gap and replacement contact schemes. Introducing silicon germanium (SiGe) superlattices and an evolutionary transistor structure, similar to horizontal gate-all-around (GAA) devices, may prove a winning combination in achieving next generation device scaling.