There are still several gaps in the EUV mask flow despite years of R&D.
Extreme ultraviolet (EUV) lithography is once again at a critical juncture. The oft-delayed technology is now being targeted for 7nm. But there are still a number of technologies that must come together before EUV is inserted into mass production at that node.
First, the EUV source must generate more power. Second, tool uptime must improve. Third, the industry needs better EUV resists. And finally, the industry still needs to address a key but sometimes overlooked part of the EUV puzzle—EUV masks and the associated infrastructure.
EUV mask technology is critical for the commercialization of EUV. The inability to develop viable and cost-effective EUV masks could be a showstopper for the technology.
The industry has been developing EUV mask technology for several years, mostly in R&D pilot lines. For high-volume production, though, the industry is making progress in some areas, but not in others. Defect review, mask blank inspection and repair are among the bright spots.
“The pieces are coming together,” said Jeff Farnsworth, director of mask technology for InteI’s captive photomask unit, dubbed Intel Mask Operation, part of the company’s Technology and Manufacturing Group.
But when asked what’s missing in the EUV mask arena, Farnsworth said: “Actinic is the big one. There are also gaps with pellicles.”
Intel is concerned about the EUV mask infrastructure, and other EUV technologies, and for good reason. “We’re serious about implementing EUV on 7nm,” he said at the recent SPIE Photomask BACUS conference. At 7nm, Intel hopes to use both EUV and multi-patterning in a complementary fashion.
Other foundry vendors also are looking to insert EUV at 7nm. And like Intel, others also see some gaps in the EUV mask infrastructure. “With EUV lithography, we need a lot more work to bring the infrastructure to maturity, particularly low-defect mask blanks,” said Harry Levinson, senior fellow and senior director of technology research at GlobalFoundries. “We need to get pattern shifting capabilities fully implemented. And we’ll need fast computational capabilities for our OPC.”
All told, the industry will need to get a handle on the EUV mask issues in order to have more realistic expectations about EUV in general. To help the industry get ahead of the curve, Semiconductor Engineering has assembled a list of some of the more challenging process steps in the EUV mask flow.
EUV and economics
ASML is readying its fourth-generation EUV tool, the NXE:3350. The 13.5nm wavelength tool has a numerical aperture of 0.33 and a resolution of 22nm half-pitch. It also consists of an 80 Watt EUV source.
In theory, EUV will simplify the patterning process. With 193nm immersion/multi-patterning, there are 34 lithography steps and 60 metrology steps at 7nm, according to Peter Wennink, president and chief executive of ASML. This compares to just 6 lithography steps and 7 metrology steps for 28nm.
With EUV, there are just 9 lithography steps and 12 metrology steps at 7nm, Wennink said. Even so, chipmakers still will require both EUV and multiple patterning at 7nm and beyond.
But based on recent breakthroughs with the EUV power source, there is a growing level of optimism for EUV, according to a new survey from the eBeam Initiative. “In general, the confidence in EUV has gone up since last year,” said Aki Fujimura, chief executive of D2S.
Still, the big question is clear. Is the EUV mask infrastructure ready for prime time? Answer: There are still several gaps in the EUV mask flow.
One of the reasons for this is the economics. It costs millions of dollars to build a tool for the EUV mask flow. Yet, there are only a few mask makers that can afford to buy these tools, making the return-on-investment rather questionable.
For example, the industry wants actinic-based EUV mask inspection technology. Using the same 13.5nm wavelength as EUV, actinic inspection can supposedly find more defects than today’s optical inspection tools.
KLA-Tencor, for one, was working on an actinic-based mask inspection tool. But the company recently put the technology on the backburner for good reason–the industry was unwilling to help pay for the R&D. In fact, it could take three to five more years to bring actinic-based mask inspection technology into the market at a cost of around $500 million.
Mask blank issues
There are other challenges as well, particularly in the EUV mask flow. The first step in the flow is to develop an EUV mask blank, which is different than today’s optical photomasks. In general, an optical mask consists of an opaque layer of chrome on a glass substrate.
In contrast, the EUV mask blank is a complex, multi-layer structure. The bottom of an EUV mask blank consists of a glass substrate. On the top of the substrate, there are 40 to 50 alternating layers of silicon and molybdenum. Then, on top of this stack, there are various and separate absorber stacks.
The EUV blank serves as a mirror or reflector for EUV light. And in theory, the EUV mask blank must be defect free.
But the problem is that EUV mask blanks are riddled with defects, such as pits and bumps, during the production process. And these defects are one of the ongoing and nagging issues with EUV masks. “The small pits introduce distortion,” said Banqiu Wu, principal member of the technical staff and chief technology officer for the Mask and TSV Etch Division at Applied Materials. “That creates phase defects.”
Over the years, mask blank vendors have reduced the number of phase defects on EUV mask blanks. In 2011, for example, there were sometimes tens of thousands of phase defects on a single blank.
In comparison, Hoya has recently developed an EUV mask blank with 3 defects at 25nm and 7 defects at 23nm. “Defect and yield control is still one of the big challenges, but the risks in defect control have been significantly reduced,” said Takahiro Onoue, general manager of the Blanks Division at Hoya.
Still, chipmakers want EUV mask blanks with even fewer defects and at higher yields. Until mask blank vendors can solve the problem, mask makers are using so-called defect mitigation strategies. One strategy is to place the defect under a stacked absorber, which resides on top of the blank.
Multi-layer phase defects in EUV masks cannot be repaired. You either have to cover them under the absorber layer, or you have to compensate for their impact. When they are exposed, it’s hard to detect them with a mask inspection tool. On top of that, it’s difficult to predict their impact on wafer.
Other issues are also surfacing. As EUV light hits the absorber stack, there is an unwanted shadowing effect. This, in turn, has prompted the industry to look at next-generation binary etched multi-layer masks.
Meanwhile, after the EUV mask blank is developed, the next step in the flow is to inspect the blank for defects using tools from Lasertec. Lasertec’s most advanced mask blank inspection tool is based on a 355nm laser light source. But optical-based mask blank inspection may lack the ability to catch all defects.
To solve this problem, Lasertec is developing an actinic-based mask blank inspection tool. Lasertec, which will ship the tool in 2016, has reported sensitivities of 15nm half-pitch. So far, the Lasertec tool is getting good reviews. “The throughput is good,” said Ted Liang, a mask technologist for the Intel Mask Operation. “The uptime is high, about 90%.”
After the inspection steps, the EUV mask blank is then sent to the photomask shop. Then, the next step in the flow is to pattern the EUV mask blank using e-beam tools.
For today’s optical masks, the trends are clear. “The patterns and the number of patterns are increasing,” said So-Eun Shin Lee, a researcher from Samsung.
That trend will continue with EUV masks. According to the eBeam mask survey, 59% of respondents predict that EUV will drive the need for complex mask shapes.
For EUV, the sub‐resolution assist feature (SRAF) sizes on the mask could range anywhere from 32nm to 40nm, compared to 60nm for optical. Or for EUV, the SRAF 1x design sizes could range anywhere from 8nm to 10nm, compared to 15nm for optical, according to Mentor Graphics. “Another thing that could change is that the OPC fragment size could shrink,” said Peter Buck, manager of MDP and platform solutions at Mentor Graphics.
As a result, EUV mask write times could jump anywhere from a whopping 50 to 100 hours per mask set, depending on the pattern density, according to experts. In comparison, for today’s optical masks, the average mask write time ranges from 8 to 15 hours per mask set, according to officials from NuFlare.
Simply put, e-beam tools may not be able to keep up with the complexity of EUV masks. As a result, photomask makers will require a new class of multi-beam e-beam mask writers. These tools consist of multiple beams, which speed up the throughputs in mask production.
Reports have surfaced, however, that the development of multi-beam e-beam mask writers is taking slightly longer than expected due to technical issues.
Still, in any case, the IMS-JEOL duo are readying the industry’s first multi-beam mask writers in the market. A beta tool is expected to ship in 2015, with a production system due out in 2016. In addition, NuFlare is also developing a multi-beam e-beam system, which is due out by the end of 2016.
Wanted: EUV inspection tools
Then, after the patterning step, the EUV mask undergoes a rigorous metrology and inspection flow. There are several possible ways to inspect EUV masks. The first choice is actinic-based mask inspection. The problem? No such tool exists.
So for now, the industry must use today’s 193nm optical inspection tools. “The best idea is to extend the existing platforms,” said Yalin Xiong, general manager of the Reticle Products Division at KLA-Tencor. “For the short term, this solution is good enough.”
There are other options on the table. E-beam inspection for EUV masks is one idea. In addition, several companies are working on multi-beam inspection. And for some time, EIDEC and Ebara have been co-developing an EUV inspection technology called a Projection Electron Microscope (PEM).
Each EUV mask inspection technology has various trade-offs. For example, optical inspection may run out of steam at some point. Moreover, e-beam can find tiny defects, but the technology is slow.
So, there is a perceived gap for EUV mask inspection. On the other hand, Intel’s Liang is upbeat about Zeiss’ actinic-based AIMS tool, which is used for defect review. “The imaging is good,” he said.
The next issue is EUV pellicles. Used in all optical masks, a pellicle is a thin-film membrane that sits on the reticle and acts as a dust cover.
At one time, the industry insisted that EUV masks did not require a pellicle. But recently, chipmakers changed their position, insisting that EUV masks now require a pellicle. Without a pellicle, according to chipmakers, the EUV reticle is prone to particles and defects.
There is a problem with EUV pellicles, however. Mask makers can’t use existing 193nm mask inspection tools, or even e-beam systems, to inspect EUV masks with the pellicle on top. The EUV pellicle itself consists of a thin polysilicon-based membrane material. Unfortunately, this material is opaque at 193nm or other wavelengths at the deep ultraviolet range.
So, what’s the solution to the problem? Answer: Develop a retractable pellicle. In fact, ASML has been developing this type of technology, which can support optical, e-beam and actinic. Still in the R&D stage, ASML’s EUV pellicle solution soon will be available in the commercial market.
“It would be nice to have a pellicle. But they need to be approached with a great deal of caution and require extensive characterization,” said GlobalFoundries’ Levinson.
“The pellicle will have to be extremely thin. There is very little volume. So the temperature goes up quite rapidly,” Levinson said. “If that pellicle breaks, and pieces of it come off, it will fall on the lenses. Those are very expensive lenses.”
All told, EUV still has several challenges. But the lowly pellicle could become the Achilles heel for EUV. “If something goes wrong (with the pellicle), the consequences are pretty catastrophic,” he added.