IP Market Shifts Direction

Experts at the table, part 3: Power-aware IP; difficulty in proving power metrics; different architectures and packaging options; debate over stacked die’s future.

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Semiconductor Engineering sat down to discuss intellectual property changes and challenges with Patrick Soheili, vice president of product management and corporate development at eSilicon; Navraj Nandra, senior director of marketing for DesignWare analog and MSIP at Synopsys; Kurt Shuler, vice president of marketing at Arteris; and Charlie Cheng, CEO of Kilopass. What follows are excerpts of that discussion. To view part 1, click here. To view part 2, click here.

SE: There was always a PPA analysis, but in the past it was weighted heavily toward performance. Is the emphasis changing?

Soheili: Performance shows up on different axes, so it’s performance in power dissipation, in die size, and in how fast it can go. But everything has a price. If you put all your energy into making it go as fast as possible, you’re going to have to have a nuclear plant next to every data center. That’s not a practical option.

Cheng: There is a new generation of devices coming out that are aimed specifically at power. Not all of them are CMOS. So there’s a huge opportunity.

Nandra: We see that. The other interesting thing is that the power control over the SoC and the IP has become really sophisticated. People are using power gating, for example, and you need to maintain certain states in the IP. You have to have a little bit of intelligence in the IP to make it work. Not only do you have to have a good story around the power of the IP, but you need intelligence to be able to go up and down with the power requirements of the SoC. Typically these SoCs have a burst of activity and then they switch off. In the past, people would just try to get the supply down, but you can’t go down any further because of physics. Now you have to switch things off and activate them. The whole design challenge is around managing the right faults and managing the latency. There’s power, there’s wake up time, and rise and fall times. The rise and fall times come into the whole EMI effect. You stop sending out energy you don’t want to send out.

Shuler: What’s happened lately is that power has become a huge selling point for technology. We started out on the largest chips, but we’re now finding ourselves in the smallest chips. They’re using harvestable power devices with sophisticated power management. But one of the things we find is that it’s hard to prove how great your power story is. That’s one of the hardest things with configurable IP. You can simulate and model it, but the techniques you use can be tougher to quantify. Finding a proof point is more difficult, which can be a problem because you may find yourself in a market you had no intention of going into.

SE: Is everything still moving onto a single SoC, or is there movement away from that again into fanouts, stacked die, and individual chips on a board?

Cheng: All of our IPs go into SoCs. An audio codec chip looks like an SoC. One of our customers created a chip at 90nm, where 90% of the die was analog. Only 10% was digital. And at 55nm, 90% is in digital and only 10% is in analog, but that 10% is the same area as the 90% was at 90nm. The amount of integration and sophistication is amazing. And that’s not a very sophisticated chip, but it has a processor, memory and lots of analog. I would call that an SoC. It’s a chip eSilicon would do. It needs some sort of fabric to manage all the different parts. It probably needs some interface IP from Synopsys. SoCs, as we define lots of different components being put into one chip, are everywhere. A power amplifier chip these days is an SoC.

Nandra: I’ve never bought into whether this an SoC or whether we go 2.5D or 3D. At every technology node we’ve seen people being able to build the stuff people said you couldn’t build. Architecturally you add a bunch of sophisticated digital stuff all around it to do the filtering. I’m seeing SoCs forever. When we think of an IP platform, is it customized IP? What customers are looking for today is support for integrating that IP onto their chip. ‘I have a 72-bit wide DDR interface. You’re selling it like this, but we want it on the chip. Can you do it for us?’ We used to say no, but we have decided to support that kind of customer. We call it a subsystem, but it actually is a complete protocol on the chip. It becomes something that is customized.

Shuler: Are you seeing more mixed-signal SoCs?

Soheili: As in the little A’s getting bigger and bigger?

Shuler: Yes, exactly. We’ve seen a little of this in the mobile space. But in the automotive space, there seems to be a bifurcation between purely digital SoCs, which are like digital hubs, but a whole bunch of mixed signal stuff going on closer to the sensors and actuators.

Soheili: We aren’t a good way to measure what’s going on in the industry. We’re selective about the customers we want to go after due to our competencies and differentiators. But our sweet spot for ASICs is 28nm, and we’re starting to build finer-geometry IPs in anticipation that migration will continue. Maybe 20% is at the older nodes. That’s where you see more bigger A’s. There is a ton of digital that keeps you busy in that domain.

Nandra: And the I/Os are mixed signal. To get to that ton of digital your USB or HDMI requires mixed signal functionality. Your codec is at 65nm, but the I/Os are becoming more mixed signal. Today it uses a PHY on the edge of the chip.

Shuler: Traditionally there’s the interface from the I/O. This is more about pressure sensors and MEMS. There is a lot of innovation there. But there also seems to be a lot of black magic and voodoo to make it all work really well, and that’s not scalable.

SE: Where is stacked die in all of this, and how does that affect IP?

Soheili: It’s a way to manage power, bandwidth, performance, and even cost, although it doesn’t seem like it in the immediate sense. But long-term it will have serious cost benefits. There also are challenges. Right now the supply chain is problematic. We don’t know who to get the right stuff from. And for those bigger companies jumping into it, they want to get their arms around the whole thing because they see it as a huge differentiator. But it’s really hard to take that pill and digest it if you’re an end customer. It’s a great opportunity with serious challenges. In terms of the IP right now, there are three memory vendors. Of those three, every one has a different flavor. A large volume graphics guy might want a second source to avoid losing their purchasing power, but how do you get two of these vendors to work with each other and commit to the same standard so the IP supplier can build something that works?

Nandra: In terms of supplying IP, there isn’t a 3D challenge. It will work in any dimension. But right now it’s not popping up as the next thing.

Shuler: For companies that own their own fabs it’s not a technology issue anymore. It’s a business model issue, a supply chain issue, who’s responsible for what. For a large IDM it’s one thing, but if you’re taking dies from two different companies it’s a business model issue.

Cheng: Like Synopsys, we’re an innocent bystander here, and 2.5D feels like Bluetooth once did. In 2005, someone was saying Bluetooth was going to take over the world. I walked out of the meeting thinking they were nuts. At the time, Bluetooth was barely hanging on because of the mobile phone, but it wasn’t everywhere. Today, no one would question it. A lot of people are debating 2.5D and 3D, particularly for how memory and DRAM are going to be aggregated. It’s a very interesting debate, but practically speaking if you look at memory chips and small form factor phones, it’s already very pervasive. It’s very entrenched as a technology. One day it will have a quantum leap and cost advantage and it will be everywhere, and we’ll be wondering why we ever debated it. It’s going to be a very viable thing.