Manufacturing Bits: Dec. 15

DRAM scaling sans EUV; high-k/metal-gate for DRAMs.

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DRAM scaling sans EUV
At the recent IEEE International Electron Devices Meeting (IEDM) in Washington, D.C., chipmakers presented papers on several technologies, including one unlikely topic—DRAM scaling.

For years, it was believed that DRAMs would hit the wall and stop scaling at 20nm or so. Then, at that point, the industry would need to migrate to a 3D DRAM structure or a next-generation memory type like MRAM.

Not so fast. At IEDM, Samsung presented a technology that would enable DRAMs at 20nm and beyond. In fact, Samsung has fabricated a 20nm DRAM without the need for extreme ultraviolet (EUV) lithography.

To enable this feat, Samsung has developed two new technologies—a honeycomb structure (HCS) and an air-spacer scheme.

“The cell capacitance can be increased by 21% at the same cell size using a novel low-cost HCS technology with one argon fluoride immersion lithography layer,” said J.M. Park, a researcher at Samsung, in a paper at IEDM. “The parasitic bit-line (BL) capacitance is reduced by 34% using an air-spacer technology whose breakdown voltage is 30% better than that of conventional technology.”

HCS is different than the traditional square structure. It is designed to maximize the capacitance at the same cell size. It makes use of a novel patterning technique using 193nm immersion lithography and multi-patterning.

“The pitch between two cell capacitors of the HCS increases by 7.5% compared to that of the square structure (SS),” Park said in the paper. “Consequently the diameter of a storage node of the HCS is 11% longer than that of the SS. Then, the HCS can generate 11% taller capacitor heights than the SS under the same HAR etching capability.”

The technology uses the same amount of dielectric material. Yet, the cell capacitance of HCS is 21% larger than the conventional technology. And on top of that, cell capacitance can be increased up to 57%, according to Samsung.

High-k/metal-gate for DRAMs
Also at IEDM, rival DRAM maker SK Hynix presented a paper on a different approach. A high-k/metal gate technology has been devised for the peripheral transistors in the DRAM.

The use of high-k/metal-gate technology material is widely used for the gate stack in logic, which is designed to reduce the gate leakage in a design.

To improve the performance of a DRAM, SK Hynix proposed to adopt high-k/metal-gate for peripheral transistors on a DRAM. “However, high thermal budgets from the DRAM cell capacitor process and high cost issues have made it difficult to implement the HKMG technology to peripheral transistors,” according to the company.

“For cost effective DRAM technology, (a) capping nitride spacer was used on (a) cell bit-line scheme, and single work function metal gate was employed without strain technology,” according to SK Hynix. “The threshold voltage was controlled by using single TiN metal gate with La2O3 and SiGe/Si epi technology. The optimized DRAM high-k/metal gate peripheral transistors showed current gains of 65%/55% and DIBL improvements of 52%/46% for nMOSFET and pMOSFET, respectively.”