Quantum computing; Intel spins devices; TFETs and III-V; Ge-on-SOI.
At this week’s IEEE International Electron Devices Meeting (IEDM) in Washington, D.C., chipmakers, research institutes and universities presented a plethora of papers on several subjects.
A large number of papers revolve around the same theme—How to extend Moore’s Law. For this, researchers are working on a number of short- and long-term technologies to propel device scaling.
Then, there are some new and different approaches, which do not adhere to classical scaling. For example, CEA-Leti has taken a step to demonstrate a quantum bit, or qubit, the building block of quantum information, in a process utilizing a silicon-on-insulator (SOI) CMOS platform.
While the leading solid-state-based approach today for treating quantum information uses superconducting qubits, there are several potential alternatives. These include semiconductor spin qubits, historically demonstrated in III-V materials, but with limited lifetime due to coupling between the electron spin and the nuclear spins of the III-V elements.
Leti and its long-time research partner Inac, a fundamental research division of CEA, are investigating an SOI technology for quantum computing with proven scalability. In this approach, quantum dots are created beneath the gates of n-type (respectively p-type) field effect transistors, which are designed to operate in the “few-electron” (respectively “few-hole”) regime at cryogenic temperatures (below 0.1 K).
Leti and Inac have developed a process for mastering control of the operation of both types of devices using Leti’s SOI nanowire FET technology. Their teams have demonstrated the co-integration and successful operation of quantum objects with conventional CMOS control electronics (standard ring oscillators) on 300mm SOI substrates.
“This technology has acquired a certain degree of robustness, and we aim at using it with very minor modifications to demonstrate qubits co-integrated with their control electronics,” said Louis Hutin, scientific staff. “This co-integration success represents a critical asset for the eventual design of a quantum computer.”
An actual qubit demonstration could be on the near horizon. The immediate next steps would be demonstrating a few (n>2) coupled qubits, and developing a strategy for long-range coupling of the qubits. It is anticipated that the built-in parallelism in the treatment of quantum information will open new perspectives for cryptography, database searching or simulation of quantum processes.
Intel spins devices
In another long-term effort, Intel, Imec and EPFL presented a paper on two types of future devices based on spintronics–spin torque majority gate and spin wave majority gate.
Spintronic logic devices are low-power, nonvolatile chips. Majority gates are devices that have a large number of inputs. They also have a large number of outputs and a certain number of control gates, according to the paper.
These types of devices have some pluses and minuses. “We find that the spin wave circuits take on average 3.5 times less area and about 400 times lower power that the equivalent circuit in CMOS,” according to the paper. “However, the spin wave circuits are on average 12 times slower.”
Spin torque majority gate has some advantages, as compared to spin wave majority gate. Spin torque majority gate uses the same materials as an MRAM.
The spin torque majority gate device resembles the shape of a cross. Each arm of the cross has a magnetic tunnel junction (MTJ). So in total, there are four MTJs.
Meanwhile, in spin wave majority gate, the structure consists of magneto-electric elements on a spin wave bus. The elements consist of a piezoelectric. They convert applied voltage to deformation and a magneto-strictive material. This, in turn, converts mechanical deformation to change in magnetization.
“Spin torque majority gates are technology friendly from a materials standpoint; however, further advances are needed to improve their performance,” according to the paper.
TFETs and III-V
In another paper at IEDM, Imec demonstrated two types of devices–gate-all-around nanowire FETs and tunnel FETs. Both devices had record-performing InGaAs materials in the channel.
Imec’s gate-all-around InGaAs nanowire FETs (Lg=50nm) performed at an average peak transconductance (gm) of 2200µS/µm with a SSSAT of 110mV/dec.
Imec increased the performance by gate-stack engineering. It used ALD and high-pressure annealing. The inter-layer/HfO2 stack achieved a 2.2 times higher gm for a device with a gate length (Lg) of 50nm, compared to the reference Al2O3/HfO2 stack.
In addition, Imec also presented a planar InGaAs homo-junction TFET with 70% indium (In) content. The increase of In content from 53% to 70% in a 8nm channel, was found to boost the performance of the device. A record ON-state current (ION) of 4µA/µm (IOFF = 100pA/µm, Vdd = 0.5V and Vd = 0.3V) with a minimum subthreshold swing (SSmin) of 60mV/dec at 300k was obtained for a planar homo-junction TFET device.
And not to be outdone, Purdue University presented a paper on a germanium (Ge) nanowire device. Using a Ge-on-insulator (GeOI) substrate, the technology demonstrates that Ge with high mobility could scale to 7nm and beyond.
In the lab, Purdue devised a hybrid Ge nanowire CMOS with an AM nFET and an IM pFET. All told, the device had channel lengths from 100nm to 40nm, a nanowire height of 10nm, and nanowire widths from 40nm to 10nm. The device also features dielectric EOTs of 2nm and 5nm.
The device also features a steep-slope of 64 mV/dec and high maximum trans-conductance (gmax) of 1057 μS/μm. The highest maximum voltage gain reaches 54 V/V.
To develop this technology, Purdue started with a Ge-on-insulator wafer from Soitec. The wafer was cleaned. Then, the nFET and pFET structures were selectively implanted.
The wafer undergoes a mesa isolation process. Then, an optimized SF6 dry etching process was applied to form the recessed channel. This was followed by another dry etching process to define the fins in the channel region. “The nanowire channel release process was carried out using 4% HF solution to selectively remove SiO2 underneath the Ge nanowire channel,” according to Purdue. “At the same time, the HF soaking could also reduce the surface damages of the nanowires caused by the dry etching process.”
For the gate dielectric, a 1nm Al2O3 film was grown using ALD. Then, a post-oxidation process was performed by rapid thermal annealing to form a 2nm GeOx underneath Al2O3. This, in turn, also activates the n- and p- dopant ions simultaneously.
“Then, recessed S/D dry etching was conducted by first striping the oxide and then partially removing the top Ge layer in the source/drain region,” according to the paper. “In following, S/D contact metal was formed by Ni deposition and ohmic annealing. Finally, the gate and interconnection metal was formed by Ni/Au.”
All lithography was carried out by a Vistec EBPG 5200 electron-beam lithography system. In total, 9 steps of lithography process were employed in the device fabrication.