tag: 3D NAND

Important Process Parameter And Its Sensitivity Check By Virtual Fabrication: Channel Hole Profile Impact On Advanced 3D NAND Structure
By Coventor - 19 Dec, 2023 - Comments: 0

A virtual DOE-based process sensitivity check was performed for two tiers of channel holes in a 3D NAND device. The channel hole tilt distance, twist angle, and their sensitivities to the visible area in silicon-oxide-nitride-oxide (SONO) punch process were analyzed. The results show that controlling the upper tilt distance is more important for offering a larger visible area. Also, a negative ... » read more

Modulated Electron Microscopy Applied In The Process Monitoring Of Memory Cell And The Defect Inspection Of Floating Circuits
By Technical Paper Link - 07 Nov, 2023 - Comments: 0

A technical paper titled “In situ electrical property quantification of memory devices by modulated electron microscopy” was published by researchers at Hitachi High-Tech Corporation, KIOXIA Corporation, and Western Digital. Abstract: "E-beam inspection based on voltage-contrast (VC) defect metrology has been widely utilized for failure mode analysis of memory devices. Variation in e-beam... » read more

Gearing Up For Hybrid Bonding
By Laura Peters - 23 Oct, 2023 - Comments: 2

Hybrid bonding is becoming the preferred approach to making heterogeneous integration work, as the semiconductor industry shifts its focus from 2D scaling to 3D scaling. By stacking chiplets vertically in direct wafer-to-wafer bonds, chipmakers can leapfrog attainable interconnection pitch from 35µm in copper micro-bumps to 10µm or less. That reduces signal delay to negligible levels and e... » read more

The Impact Of Channel Hole Profiles On Advanced 3D NAND Structures
By Qingpeng Wang - 19 Oct, 2023 - Comments: 0

In a two-tier 3D NAND structure, the upper and lower channel hole profile can be different, and this combination of different profiles leads to different top-down visible areas. The visible area is the key metric to determine whether the bottom SONO layer can be punched through and ensure that the bit cells connect to the common source line. Performing channel hole profile splits on a silicon w... » read more

3D NAND Needs 3D Metrology
By Nick Keller - 08 Aug, 2023 - Comments: 0

By Nick Keller and Andy Antonelli You’ve read the reports: the memory market is floundering as the semiconductor industry moves through another scarcity/surplus cycle. Be that as it may, innovation is happening as the industry continues to pursue increasingly higher three-dimensional stacks, with 3D NAND stacks taller than 200 layers entering production. However, there are challenges... » read more

Demonstrating The Capabilities Of Virtual Wafer Process Modeling And Virtual Metrology
By Technical Paper Link - 27 Jul, 2023 - Comments: 0

A technical paper titled “Review of virtual wafer process modeling and metrology for advanced technology development” was published by researchers at Coventor Inc., Lam Research. Abstract: "Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the p... » read more

Week In Review: Semiconductor Manufacturing, Test
By Gregory Haley - 16 Jun, 2023 - Comments: 0

Applied Materials sued its Chinese-owned rival, Mattson, over an alleged 14-month effort to steal valuable trade secrets, reports Bloomberg. In court filing, Applied Materials claimed that Mattson engaged in a spree of employee-poaching and covertly transferring semiconductor equipment designs. Global semiconductor materials revenue grew 8.9% to $72.7 billion in 2022, surpassing the previous... » read more

3D Memory Structures: Common Hole And Tilt Metrology Techniques and Capabilities
By Technical Paper Link - 03 Jun, 2023 - Comments: 0

A technical paper titled "Inline metrology of high aspect ratio hole tilt and center line shift using small-angle x-ray scattering" was published by researchers at Bruker Nano and Lam Research. Abstract: "High aspect ratio (HAR) structures found in three-dimensional nand memory structures have unique process control challenges. The etch used to fabricate channel holes several microns deep... » read more

Etch Processes Push Toward Higher Selectivity, Cost Control
By Laura Peters - 18 May, 2023 - Comments: 0

Plasma etching is perhaps the most essential process in semiconductor manufacturing, and possibly the most complex of all fab operations next to photolithography. Nearly half of all fab steps rely on a plasma, an energetic ionized gas, to do their work. Despite ever-shrinking transistor and memory cells, engineers continue to deliver reliable etch processes. “To sustainably create chips... » read more

How Metrology Tools Stack Up In 3D NAND Devices
By Laura Peters - 15 May, 2023 - Comments: 0

Multiple innovations in semiconductor processing are needed to enable 3D NAND bit density increases of about 30% per year at ever-decreasing cost per bit, all of which will be required to meet the nonvolatile storage needs of the big data era. 3D NAND is the first truly three-dimensional device in production. It is both a technology driver for new metrology methods and a significant part of ... » read more

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