Supporting CPUs Plus FPGAs

While it has been possible to pair a CPU and FPGA for quite some time, two things have changed recently. First, the industry has reduced the latency of the connection between them and second, we now appear to have the killer app for this combination. Semiconductor Engineering sat down to discuss these changes and the state of the tool chain to support this combination, with Kent Orthner, system... » read more

Towards A Metric To Measure Verification Computing Efficiency

Thinking back about DAC 2015 in San Francisco earlier this month, I am happy that at least some of my predictions came true—there was clearly a trend towards making verification smarter. However, one thing struck me while hearing all the discussions on connecting engines is what Jim Hogan called the continuum of verification engines (COVE)—and what we at Cadence call the system development ... » read more

Toward Smarter Design Automation

In less than two weeks, the EDA industry will convene for its biggest conference of the year, the Design Automation Conference, again in San Francisco. Last year, I “came clean” with a post called “Confessions Of An ESL-Aholic,” pointing out that beyond high-level synthesis, a significant shift towards a more abstract design description than RTL has not yet happened and that a lot of th... » read more