tag: cache coherence

Reducing The Cost of Cache Coherence By Integrating HW Coherence Protocol Directly With The Programming Language
By Technical Paper Link - 19 Mar, 2023 - Comments: 0

A new technical paper titled "WARDen: Specializing Cache Coherence for High-Level Parallel Languages" was published by researchers at Northwestern University and Carnegie Mellon University. Abstract: "High-level parallel languages (HLPLs) make it easier to write correct parallel programs. Disciplined memory usage in these languages enables new optimizations for hardware bottlenecks, such ... » read more

Manycore-FPGA Architecture Employing Novel Duet Adapters To Integrate eFPGAs in a Scalable, Non-Intrusive, Cache-Coherent Manner (Princeton)
By Technical Paper Link - 16 Jan, 2023 - Comments: 0

A technical paper titled "Duet: Creating Harmony between Processors and Embedded FPGAs" was written by researchers at Princeton University. Abstract "The demise of Moore's Law has led to the rise of hardware acceleration. However, the focus on accelerating stable algorithms in their entirety neglects the abundant fine-grained acceleration opportunities available in broader domains and squan... » read more

Hardware Trojans Target Coherence Systems in Chiplets (Texas A&M / NYU)
By Technical Paper Link - 01 Dec, 2022 - Comments: 0

A technical paper titled "Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems" was published by researchers at Texas A&M University and NYU. Abstract: "As industry moves toward chiplet-based designs, the insertion of hardware Trojans poses a significant threat to the security of these systems. These systems rely heavily on cache coherence for coherent data communic... » read more

Foundational Changes In Chip Architectures
By Brian Bailey - 13 Oct, 2022 - Comments: 5

We take many things in the semiconductor world for granted, but what if some of the decisions made decades ago are no longer viable or optimal? We saw a small example with finFETs, where the planar transistor would no longer scale. Today we are facing several bigger disruptions that will have much larger ripple effects. Technology often progresses in a linear fashion. Each step provides incr... » read more

The Automotive Paradigm Shift
By Frank Schirrmeister - 06 Oct, 2022 - Comments: 0

We are currently experiencing a pivotal moment concerning the automotive industry. Three major technology areas are converging. First, there is an enormous demand for advanced driver-assistance systems (ADAS) coupled with the increasing trend toward autonomy. Second is the digitization and electrification of everything, which is driving the need for efficient compute. Third is the trend to high... » read more

Moving From AMBA ACE to CHI For Coherency
By Min Lei - 09 Dec, 2021 - Comments: 1

Introduced back in 2011, ACE (AXI Coherency Extensions) grew from the existing AXI protocol to satisfy the cache coherency maintenance demands of SoCs with multi core processors and shared caches in smart phones, mobile computers, and servers. It added new channels for cache communication, extra signals to allow new transaction for coherency support, and five state model for caches. AXI + A... » read more

CXL Vs. CCIX
By Ed Sperling - 06 Dec, 2019 - Comments: 0

Kurt Shuler, vice president of marketing at ArterisIP, explains how these two standards differ, which one works best where, and what each was designed for. » read more

How To Integrate An Embedded FPGA
By Brian Bailey - 30 May, 2019 - Comments: 1

Choosing to add programmable logic into an SoC with an eFPGA is just the beginning. Other choices follow involving how many lookup tables (LUTs), how much routing and what topology, how will data be transferred in and out of the fabric, does data need to be coherent with system memory, how will it be programmed and tested, and what RTL functions need to be embedded into the programmable fabric ... » read more

Got System Cache?
By Rajesh Ramanujam - 25 Aug, 2016 - Comments: 0

Similar to the world we live in, a coherent SoC system has truly become a hodgepodge of often conflicting desires, wants, and needs. While some traffic flows are highly sensitive to CAS latency, others have rigid coherent bandwidth requirements, and others are more concerned with “must have” real-time needs to fulfill their tasks. Varying vastly from "must haves" to "best-effort," finding t... » read more

System-Level Verification Tackles New Role
By Brian Bailey - 28 Apr, 2016 - Comments: 0

Wally Rhines, chairman and CEO of Mentor Graphics, gave the keynote at DVCon this year. He said that if you pull together a bunch of pre-verified IP blocks, it does not change the verification problem at the system level. That sounds like a problem. There are assumptions made that the IP blocks work to a reasonable degree, and that when performing system-level verification the focus is not a... » read more

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