Got System Cache?

Similar to the world we live in, a coherent SoC system has truly become a hodgepodge of often conflicting desires, wants, and needs. While some traffic flows are highly sensitive to CAS latency, others have rigid coherent bandwidth requirements, and others are more concerned with “must have” real-time needs to fulfill their tasks. Varying vastly from "must haves" to "best-effort," finding t... » read more

System-Level Verification Tackles New Role

Wally Rhines, chairman and CEO of Mentor Graphics, gave the keynote at DVCon this year. He said that if you pull together a bunch of pre-verified IP blocks, it does not change the verification problem at the system level. That sounds like a problem. There are assumptions made that the IP blocks work to a reasonable degree, and that when performing system-level verification the focus is not a... » read more

System Bits: Sept. 15

Cache-coherence innovation for thousand-core chips MIT researchers are getting ready to unveil what they say is the first fundamentally new approach to cache coherence in more than three decades. They reminded that in a modern, multicore chip, every processor core has its own small memory cache, where it stores frequently used data. The chip also has a larger, shared cache, which all the cores... » read more

The Evolving Interconnect

By Ann Steffora Mutschler Chip interconnect protocol requirements are evolving as designs move to 20nm and below process geometries, and not always in predictable ways. At least part of this is being driven by what an SoC is used for. The continued push to shrink features opens up real estate at each new process node. For the past decade, that real estate has been used to add more featu... » read more