How Long Will FinFETs Last?


Semiconductor Engineering sat down to discuss how long [getkc id="185" kc_name="FinFET"]s will last and where we will we go next with Vassilios Gerousis, Distinguished Engineer at [getentity id="22032" e_name="Cadence"]; Juan Rey, Sr. Director of Engineering for Calibre R&D at [getentity id="22017" e_name="Mentor Graphics"]; Kelvin Low, Senior Director Foundry Marketing at [getentity id="22... » read more

How Long Will FinFETs Last?


Semiconductor Engineering sat down to discuss how long FinFETs will last and where we will we go next with Vassilios Gerousis, Distinguished Engineer at [getentity id="22032" e_name="Cadence"]; Juan Rey, Sr. Director of Engineering for Calibre R&D at [getentity id="22017" e_name="Mentor Graphics"]; Kelvin Low, Senior Director Foundry Marketing at [getentity id="22865" e_name="Samsung"]; and Vic... » read more

Unraveling The Mysteries At IEDM


In some respects, the 2014 IEEE International Electron Devices Meeting (IEDM) was no different than past events. The event, held this week in San Francisco, included the usual and dizzying array of tutorials, sessions, papers and panels. On the leading-edge CMOS front, for example, the topics included [getkc id="82" kc_name="2.5D"]/[getkc id="42" kc_name="3D IC"] chips, III-V materials, [getkc ... » read more

Manufacturing Bits: Oct. 21


Peanut butter and chocolate TEMs Lawrence Livermore National Laboratory, Johns Hopkins University and the National Institute of Standards and Technology (NIST) have developed a new microscopy technology that combines two types of key measurements. The technology, dubbed the dynamic transmission electron microscope (DTEM), captures information about both temperature and the crystal structure... » read more

Executive Insight: Luc Van den hove


Semiconductor Engineering sat down to discuss current and future process technology challenges with Luc Van den hove, president and chief executive of Imec. What follows are excerpts of that conversation. SE: The industry is simultaneously working on several new and expensive technologies. This includes extreme ultraviolet (EUV) lithography and the next-generation 450mm wafer size. The indu... » read more

Tunnel FETs Emerge In Scaling Race


Traditional CMOS scaling will continue for the foreseeable future, possibly to the 5nm node and perhaps beyond, according to many chipmakers. In fact, chipmakers already are plotting out a path toward the 5nm node, but needless to say, the industry faces a multitude of challenges along the road. Presently, the leading transistor candidates for 5nm are the usual suspects—III-V finFETs; gate... » read more

Manufacturing Bits: Oct. 1


Nanoimprint Foundry Singapore’s A*STAR’s Institute of Materials Research and Engineering (IMRE) and its partners have launched a new R&D foundry using nanoimprint lithography. The so-called Nanoimprint Foundry is a collaboration between several entities, such as IMRE, Toshiba Machines, EV Group, NTT, NIL Technology, Kyodo International, Micro Resist Technology, Nanoveu and Solves In... » read more