Culture Clash In Analog


The analog/mixed signal world is being shaken up by a mix of new tools, an influx of younger engineers with new and broader approaches, and an emphasis on changing methodologies to improve time to market. Analog and digital engineers have never quite seen eye-to-eye. Analog teams leverage techniques that have been around, in some cases, for decades, while digital teams rely heavily on the la... » read more

Filling In The Gaps For Mixed-Signal Verification


Semiconductor Engineering sat down to discuss mixed-signal verification with Haiko Morgenstern, Mixed-Signal Verification Group Staff Engineer at Infineon; Dr. Gernot Koch, CAD Manager at Micronas; Pierluigi Daglio, AMS Design Verification Flows Manager at STMicroelectronics; and Helene Thibieroz, AMS marketing manager at [getentity id="22035" e_name="Synopsys"]. What follows are excerpts of th... » read more

Filling In The Gaps For Mixed-Signal Verification


Semiconductor Engineering sat down to discuss mixed-signal verification with Haiko Morgenstern, Mixed-Signal Verification Group Staff Engineer at Infineon; Dr. Gernot Koch, CAD Manager at Micronas; Pierluigi Daglio, AMS Design Verification Flows Manager at STMicroelectronics; and Helene Thibieroz, AMS marketing manager at [getentity id="22035" comment="Synopsys"]. What follows are excerpts of t... » read more

Filling In The Gaps For Mixed-Signal Verification


Semiconductor Engineering sat down to discuss mixed-signal [getkc id="10" kc_name="Verification"] with Haiko Morgenstern, Mixed-Signal Verification Group Staff Engineer at Infineon; Dr. Gernot Koch, CAD Manager at Micronas; Pierluigi Daglio, AMS Design Verification Flows Manager at STMicroelectronics; and Helene Thibieroz, AMS marketing manager at [getentity id="22035" comment="Synopsys"]. What... » read more

Solutions For Mixed-Signal SoC Verification Using Real Number Models


As old methods fall short, new techniques make advanced SoC verification possible. This paper presents mixed-signal block and IC-level verification methodologies using analog behavioral modeling and combined analog and digital solvers. It then describes analog real number modeling (RNM) and how it is used in top-level SoC verification. To view this white paper, click here. » read more

Solutions For Mixed-Signal SoC Verification


Performing full-chip verification of large mixed-signal systems on chip (SoCs) is an increasingly daunting task. As complexity grows and process nodes shrink, it’s no longer adequate to bolt together analog or digital “black boxes” that are presumed to be pre-verified. Complex analog/ digital interactions can create functional errors, which delay tapeouts and lead to costly silicon re-spi... » read more

Physical Effects Affecting Design


With the increase in analog content in today’s designs, the industry is facing a real challenge in terms of how to perform mixed-signal verification at the functional level, at the SPICE level and down to physical implementation of the DRC rules. Joseph Davis, product manager for Calibre interactive and integration products at Mentor Graphics, explained there are three things driving what... » read more