tag: NRZ

DSP Techniques For High-Speed SerDes
By Ed Sperling - 23 Oct, 2023 - Comments: 0

Sensors everywhere, more connected devices, and the rollout of smart everything has created a flood of data. The question now is how to best handle all of that data, where to process it, and how to move it locally and to the outside network. Madhumita Sanyal, technical product manager at Synopsys, talks about the need for continuous performance improvements in SerDes, PCIe, NRZ, and PAM4, and w... » read more

Advanced Modulation And Coding Challenges
By Keysight - 22 Feb, 2023 - Comments: 0

Demands for a connected world with instant data access continue to drive data center transceiver innovation. 100 gigabit Ethernet (GE) data transmission is in production and will continue to evolve. But 100GE speeds aren’t fast enough to support the expected surge in connected devices and the applications they will run, opening the door for 400GE. Non-return-to-zero (NRZ) and four-level pulse... » read more

Getting Ready For An Efficient Shift To PCI Express 6.0 Designs With Optimized IP
By Gary Ruggles - 10 Jun, 2021 - Comments: 0

PCI Express (PCIe) 6.0 technology with key changes will bring about challenges that high-performance computing, artificial intelligence, and storage system-on-chip (SoC) designers will face. This article provides designers a summary of the major changes and how they can be handled to ensure a smooth and successful transition to PCIe 6.0. The three major changes in PCIe 6.0 that designers nee... » read more

Enabling Cost-Effective, High-Performance Die-to-Die Connectivity
By Thomas Wong - 09 Jul, 2020 - Comments: 0

System advances in accelerated computing platforms such as CPUs, GPUs and FPGAs, heterogeneous systems on chip (SoCs) for AI acceleration and high-speed networking/interconnects have all pushed chip integration to unprecedented levels. This requires more complex designs and higher levels of integration, larger die sizes and adopting the most advanced geometries as quickly as possible. Facing th... » read more

High-Speed Signaling Drill-Down
By Bryon Moyer - 17 Jun, 2020 - Comments: 0

Chip interconnect standards have received a lot of attention lately, with parallel versions proliferating for chiplets and serial versions moving to higher speeds. The lowliest characteristic of these interconnect schemes is the physical signaling format. Having been static at NRZ (non-return-to-zero) for decades, change is underway. “Multiple approaches are likely to emerge,” said Brig ... » read more

Die-To-Die Connectivity
By Ed Sperling - 22 Nov, 2019 - Comments: 0

Manmeet Walia, senior product marketing manager at Synopsys, talks with Semiconductor Engineering about how die-to-die communication is changing as Moore’s Law slows down, new use cases such as high-performance computing, AI SoCs, optical modules, and where the tradeoffs are for different applications.   Interested in more Semiconductor Engineering videos? Sign-up for our YouTu... » read more

Wrestling With High-Speed SerDes
By Ann Mutschler - 19 Jun, 2019 - Comments: 2

SerDes has emerged as the primary solution in chips where there is a need for fast data movement and limited I/O, but this technology is becoming significantly more challenging to work with as speeds continue to rise to offset the massive increase in data. A Serializer/Deserializer is used to convert parallel data into serial data, allowing designers to speed up data communication without h... » read more

M2M’s Network Impact
By Ed Sperling - 25 Jul, 2018 - Comments: 0

Synopsys’ Manmeet Walia talks examines the impact of machine-to-machine traffic and why that requires some fundamental changes in networking architectures. Two key issues that need to be addressed are scalability and latency, which require new networking architectures. https://youtu.be/2RIQt3QVPtE » read more

Understanding SerDes Signal Integrity Challenges
By Bill Fuller - 13 Apr, 2017 - Comments: 0

Signal integrity (SI) can perhaps best be defined as a set of measures of the quality of electrical signals, which are subject to the effects of noise, distortion and loss. Additional signal integrity issues include jitter, ringing, crosstalk, ground bounce and power supply noise. There are multiple factors that can negatively influence signal integrity, thereby causing errors and system fai... » read more

SerDes Signal Integrity Challenges At 28Gbps And Beyond
By Rambus - 12 Apr, 2017 - Comments: 0

After nearly fifty years, NRZ technology continues to pose significant challenges as data rates approach 56Gbps and refreshed standards mandate increased receiver sensitivity (down to 35 mV). With shorter unit intervals and closing eyes, triggering becomes ever more complex and requires enhanced receiver equalization such as continuous-time-linear equalization and decision feedback equalization... » read more

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