Which Verification Engine?


Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

The Week In Review: Design


Tools Imperas debuted its RISC-V Processor Developer Suite, a set of models, a software simulator, and tools to validate, verify, and provide early estimation of timing performance and power consumption for RISC-V processors. IP Minima Processor revealed its dynamic-margining subsystem IP for near-threshold voltage design. The startup's hardware and software IP works with a CPU or DSP proc... » read more

Prototyping Partitioning Problems


Gaps are widening in the prototyping of large, complex chips because the speed and capacity of the FPGA is not keeping pace with rapid rollout pace of advanced ASICs. This is a new twist for a well-established market. Indeed, prototyping with FPGAs is as old as the [gettech id="31071" t_name="FPGAs"] themselves. Even before they were called FPGAs, logic accelerators or LCAs (logic cell ar... » read more

The Uncontrolled Rise Of Functional Safety Standards


Over the past 30 years, advances in software and hardware have made it possible to create sophisticated systems controlling crucial aspects of complex equipment, from rolling and pitching in aircrafts, to steering and braking in cars. The processes and methods defined in functional safety standards are crucial to ensure that these systems behave as expected and safely, even when certain parts â... » read more

Could Liquid IP Lead To Better Chips?


Semiconductor Engineering sat down to discuss the benefits that could come from making IP available as abstract blocks instead of RTL implementations with Mark Johnstone, technical director for Electronic Design Automation for [getentity id="22499" e_name="NXP"] Semiconductor; [getperson id="11489" p_name="Drew Wingard"], CTO at [getentity id="22605" e_name="Sonics"]; Bryan Bowyer, director of ... » read more

Which Verification Engine?


Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

How To Handle Concurrency


The evolution of processing architectures has solved many problems within a chip, but for each problem solved another one was created. Concurrency is one of those issues, and it has been getting much more attention lately. While concurrency is hardly a new problem, the complexity of today’s systems is making it increasingly difficult to properly design, implement and verify the software an... » read more

Look Ma, No Hands! Functional Safety From The Driver’s Seat


Every so often, I undertake a project that reminds me why I love working in semiconductor marketing. Back in August, I hopped behind the wheel of a Tesla Model X to film a video for OneSpin about how formal verification can help designers to satisfy the ISO 26262 automotive safety standard. If you haven't yet seen the video, you can watch it here: http://bit.ly/2ycK5Yp The Model X itself was... » read more

Prototypes Proliferate


Hardware prototyping and [getkc id="30" kc_name="emulation"] have been two sides of the same coin ever since the [gettech id="31071" comment="FPGA"] became a commercial success. Early emulators were all built from FPGAs, and most were used in-circuit, much like prototypes are today. More recently, emulation has become a major piece of the [getkc id="10" kc_name="verification"] flow, to the poin... » read more

System Coverage Undefined


When is a design ready to be taped out? That has been one of the toughest questions to confront every design team, and it's the one verification engineers lose sleep over. Exhaustive [getkc id="56" kc_name="coverage"] has not been possible since the 1980s. Several metrics and methodologies have been defined to help answer the question and to raise confidence that important aspects of a block... » read more

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