SRAM Physical Verification With Calibre Pattern Matching

Traditional SRAM verification flows can require significant resources to implement and support, and still miss critical errors that result in manufacturing defects. Using the Calibre Pattern Matching automated pattern-based solution provides accurate results, avoids costly mask re-spins, and is easily updated to add newly developed SRAM IP cells. To read more, click here. » read more

Pattern Matching In Test And Yield Analysis

By Jonathan Muirhead and Geir Eide It’s no secret that a successful yield ramp directly impacts integrated circuit (IC) product cost and time-to-market. Tools and techniques that help companies ramp to volume faster, while also reducing process and design variability, can be the difference between profit and loss in a competitive market. And while pattern matching technology has been aroun... » read more

A Pattern Of Success: Calibre Pattern Matching

Calibre Pattern Matching allows you to define specific geometric configurations as visual patterns, directly from a design layout. With this visual representation, Calibre Pattern Matching opens up a whole new way to define design rules for both established and advanced nodes, and enables a wide range of innovative applications across design, verification, and test. This white paper introduces ... » read more

Pattern Matching in Design and Verification

Pattern matching (PM) was first introduced as the semiconductor industry began to shift from simple one-dimensional rule checks to the two-dimensional checks required by sub-resolution lithography. These rule checks proved far more complex to write, hard to code for fast runtimes, and difficult to debug. Incorporating an automated visual capture and compare process enabled designers to define t... » read more

Analog Design And Pattern Matching: A Perfect Pairing

While automated pattern matching is widely used in the digital IC physical verification process, adoption in the analog space has been much slower. In fact, the very nature of customized analog circuits lends itself ideally to some of the newer physical verification techniques offered by automated pattern matching technology, enabling designers to reduce verification time while still ensuring d... » read more

Capacity Constraints And DFM At Mature Nodes

We’re witnessing an interesting phenomenon in the SoC segment of the semiconductor industry today. One might call it the “forced waterfall effect.” What I’m referring to is the tendency for production at semiconductor nodes older than the leading edge to be under long-term foundry capacity constraints. Normally this occurs with the “hot process node,” that is, the leading edge wh... » read more

Pattern Matching: Blueprints For Further Success

Design patterns have a wide variety of applications in the design, verification and test flows of IC development. From significantly reducing rule deck complexity to simplifying the task of avoiding known yield detractors to enhancing workflows such as design rule waiver recognition, pattern matching has become a useful tool throughout design, verification, and test process. Learn how Calibre P... » read more

Good Pattern Flow Ahead For 14, 10nm

By Ann Steffora Mutschler Given complexity, yield, power and other challenges with leading edge manufacturing, semiconductor foundries increasingly have been forced to require more and more restrictive design rules with each new process node. “They keep adding more design rules and more operations to a particular check to eliminate corner cases where in manufacturing they saw some variant... » read more

Reducing The Drama In DFM

By Ann Steffora Mutschler For reducing cycle time of DFM checks prior to manufacturing, pattern matching is a topic of great excitement as of the past few manufacturing nodes. The idea behind the technology is that there are certain patterns in the physical layout of the chip, which unless they are addressed, won’t come out right. That’s what causes the drama, observed Saleem Haider, se... » read more

A Hybrid Model/Pattern-Based OPC Approach For Improved Consistency And TAT

As the technology advances, OPC run time turns to be a big concern, and a great deal of our effort is directed toward speeding up the litho operations. In addition, the OPC simulation consistency sometimes deteriorates, which is a critical issue—especially for anchor features. On the other hand, full-chip designs usually comprise large arrays of basic cells, used by OPC engineers to tune OPC ... » read more