Device Pin-Specific Property Extraction For Layout Simulation


As we work through the sub-20 nm design space, the interactions between and effects on devices that are near each other are becoming critical factors in achieving the desired electrical performance. Accurate extraction of device pin-specific properties for modelling these effects is essential to attaining design goals. LVS extraction challenges Layout vs. schematic (LVS) comparison tools prov... » read more

What’s Holding Back Analog?


The uneasy relationship between digital and analog, coupled with tools that are either ineffective or outright ignored by the analog community, may be limiting the growth potential and technological advances in that market. That certainly doesn’t mean analog isn’t growing. In fact, analog is an increasingly critical component of ICs and the electronic devices they inhabit. The global ele... » read more

Intento Design


While the United States is where most EDA developments have come from, there have been pockets of success at various places around the world and one that has produced more than most in recent years in France. Semiconductor Engineering spoke with [getperson id=" 11759 " comment ="Ramy Iskander"], founder and CEO and Eric Laurent, worldwide sales and business development for [getentity id="22905"... » read more

Problems Ahead For EDA


You may have discovered that the Semiconductor Engineering Knowledge Center (KC) provides various ways in which data can be viewed. One way is to see what events happened in a given year. During the 1990s, company activity in terms of new startups and acquisitions reached a peak, and in 1997 there were at least 29 startups that the KC contains and 25 companies acquired (let us know if there wer... » read more

Package Modeling Needs For A Robust IC Power Integrity Sign-Off


Progress in IC technology has allowed chip designers to pack more functionality and continually make better use of silicon area. This trend, coupled with the need to maintain low power using techniques such as voltage islands and power and clock gating, has caused the power consumption to vary across the chip and over time. This has introduced considerable amount of transient current peaks in t... » read more

Conflicting Needs For IoT Edge Designs


The mad rush has begun to hype the [getkc id="76" comment="Internet of Things"], but the path forward isn't quite as straightforward as the marketers would like it to be. ICs used at the edge of the IoT—the ones that gather information to be controlled by smart phones or tablets and transmitted to devices for processing and data analytics—need to be designed differently than the initial for... » read more

Standards Watch


This may sound odd to anyone outside of the SoC world, but as more functionality and more components move from PCB to chip—or at least the same package—what’s happening in the standards world is mirroring what’s going on in semiconductor design and manufacturing. The rule of thumb in the standards world is that as new techniques and technologies are introduced, the number of standard... » read more

Improving Design Reliability By Avoiding Electrical Overstress


Electrical overstress (EOS) is one of the leading causes of IC failures across all semiconductor manufacturers, and is responsible for the vast majority of device failures and product returns. The use of multiple voltages increases the risk of EOS, so IC designers need to increase their diligence to ensure that thin-oxide digital transistors do not have direct or indirect paths to high-voltage ... » read more

Experts At The Table: The Growing Signoff Headache


By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss signoff issues with Rob Aitken, an ARM fellow; Sumbal Rafiq, director of engineering at Applied Micro; Ruben Molina, product marketing director for timing signoff at Cadence; Carey Robertson, director of product marketing for Calibre extraction at Mentor Graphics; and Robert Hoogenstryd, director of marketing for design ... » read more

Sprint To The Finish Line


By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss future challenges, pain points, and how the supply chain is being reconfigured with Chi-Ping Hsu, senior vice president for R&D in the Silicon Realization Group at Cadence. What follows are excerpts of that conversation. LPHP: Has the move to 20nm processes with 14nm finFETs progressed as smoothly as everyone hop... » read more

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