What’s The Real Benefit Of High-Level Synthesis?


Once upon a time, “behavioral synthesis,” the precursor to high-level synthesis, hung its hat on design productivity as its sole value. By that, I mean, if a behavioral synthesis tool provides a high enough productivity benefit, designers or design managers will boil the ocean to move to it. There was little methodology around it. In fact, even the design entry language was unfamiliar. Yes,... » read more

The Time Dimension Of Power


Power is the flow of energy over time. While both aspects of that equation are important, they are important to different people in different ways. Energy that moves too quickly can cause significant damage. Too much energy moving over time can mean a non-competitive product, from battery-powered devices to a wide array of locations such as the datacenter. When the industry talks about power... » read more

Three Power-Saving Techniques Using PCI Express IP


The increasing data traffic between devices in a computing application environment is causing a large power footprint, and for that reason designers are looking for ways to lower the power consumption of their SoCs during sparse or idle times. The smaller, battery-powered devices are often idle and in deep sleep modes, but these deep power saving modes come at the cost of slow resume times to s... » read more

Optimization Challenges For 10nm And 7nm


Optimization used to be a simple timing against area tradeoff, but not anymore. As we go to each new node the tradeoffs become more complicated, involving additional aspects of the design that used to be dealt with in isolation. Semiconductor Engineering sat down to discuss these issues with Krishna Balachandran, director of product management for low-power products at [getentity id="22032"... » read more

System-Level Verification Tackles New Role


Semiconductor Engineering sat down to discuss advances in system-level verification with Larry Melling, product management director for the system verification group of [getentity id="22032" e_name="Cadence"]; Larry Lapides, VP of sales for [getentity id="22036" e_name="Imperas”] and Jean-Marie Brunet, director of marketing for the emulation division of [getentity id="22017" e_name="Mentor Gr... » read more

Reflections On 2015


It is easy to make predictions, but few people can make them with any degree of accuracy. Most of the time, those predictions are forgotten by the end of the year and there is no one to do a tally of who holds more credibility for next year. Not so with SemiEngineering. We like to hold people's feet to the fire, but while the Pants-On-Fire meter may be applicable to politicians, we like to thin... » read more

Leveraging Physically Aware Design-For-Test To Improve Area, Power, And Timing


Increased pressures on design teams to deliver faster, smaller devices in less time has required EDA companies to develop an integrated methodology to incorporate physical design information during DFT synthesis. This solution must consider the placeable area (or size) of the circuit as well as routing blockages and hard macro placement locations. It must also be able to both model the wiring i... » read more

Cracking The Tough Nut Using Formal Methods


Pranav Ashar, CTO of Real Intent, assured a packed room of researchers and practitioners of formal methods at the recent FMCAD conference: “Static verification is being used in the verification of designs. Every major chip out there is using static methods for sign-off today.” He used an analogy of cracking a nut. “There’s a right way and a wrong way and if you don’t pick the right me... » read more

Combining Power And Synthesis


By Ann Steffora Mutschler Each passing design node shrinks electronic designs ever smaller and more complex, which has made power management a critical design priority – even in the synthesis step in the design flow. Synthesis has always been an integral part of the design process, particularly at the RTL level. But as chip design has become more complicated, the need to raise the pro... » read more

Synthesis: Next Steps In SoC Design


Five experts sound off to System-Level Design on the state of synthesis and what's needed in the future: Shawn McCloud, product line director for Catapult C Synthesis at Mentor Graphics; Chris Eddington, director of marketing for system-lvel products at Synopsys; Brett Cline, VP of marketing at Forte Design Systems; Andy Biddle, director of business development at Magma and Sanjiv Kaul, executi... » read more

← Older posts