tag: verification IP

Making Verification Easier
By Ann Mutschler - 28 Jul, 2016 - Comments: 0

SoC design teams increasingly are confronting complexity in the quest to target application segments, but at the same time they are struggling to more quickly reduce risk in their designs while also speed up testing to make sure everything works. Those often-conflicting goals have transformed [getkc id="10" kc_name="verification"] IP from an interesting concept to a must-have tool for advanc... » read more

Debug Becomes A Bigger Problem
By Brian Bailey - 11 Feb, 2016 - Comments: 3

The EDA industry has invested enormous amounts of time and energy on the verification process, including new languages, new tools, new class libraries, new methodologies. But the one part of the cycle that defines that type of automation is debug. Development teams are spending half of their time in the debug process and the problem is growing. Part of the reason is that design and debug are... » read more

Will The Chip Work?
By Ed Sperling - 26 Oct, 2015 - Comments: 0

As the number of possible issues mount for integrating IP into complex chips, so does the focus on solving these issues. What becomes quickly apparent to anyone integrating multiple IP blocks is that one size doesn't fit all, either from an IP or a tools standpoint. There is no single solution because there is no single way of putting IP together. Each architecture is unique, and each brings... » read more

Will The Chip Work?
By Ed Sperling - 19 Oct, 2015 - Comments: 1

IP is getting better, but the challenges of integrating it are getting worse. As the number of IP blocks in SoCs increases at each new process node, so does the difficulty of making them all work together. In some cases, this can mean extra code and a slight performance hit on power and performance. In other cases, it may require more drastic measures, ranging from a re-spin to a new archite... » read more

Tech Talk: SoC Protocol Debug
By Ed Sperling - 24 Sep, 2015 - Comments: 0

Bernie DeLay, group director for verification IP R&D at Synopsys, talks about what goes wrong in complex SoCs, how so-called standard pieces play together, and where are the gotchas in re-use. [youtube vid=AaY_AmdjUpo] » read more

ESL: 20 Years Old, 10 To Go
By Brian Bailey - 23 Sep, 2015 - Comments: 2

It is a common perception that the rate of technology adoption accelerates. In 1873, the telephone was invented and, after 46 years, it had been adopted by one-quarter of the U.S. population. Television, invented in 1926 took 26 years. The PC in 1975 took just 16 years. It took only 7 years after the introduction of the Internet in 1991 before it was seeing significant levels of adoption. So... » read more

HDMI 2.0 Design And Verification Challenges
By Cadence - 11 Mar, 2015 - Comments: 0

High-Definition Multimedia Interface (HDMI) is an audio/video (A/V) trans- mission protocol, which is omnipresent in consumer electronics, personal computing, and mobile products. Modern-day requirements of big screen resolutions, 3D, and multi-channel/multi-stream audio have pushed display devices to use a completely digital, high-speed transmission media, requiring a multi-layered protocol li... » read more

The Week In Review: Design/IoT
By Ed Sperling - 12 Dec, 2014 - Comments: 0

Tools Cadence rolled out a use-case scenario verification tool that automates some test development that has been done manually in the past. The new tool accelerates development of software-driven tests and debug to ferret out complex SoC-level bugs. Cadence claims a 10X productivity improvement. Mentor Graphics uncorked a new version of its verification IP for PCI Express. The new IP decre... » read more

The Week In Review: Design
By Ed Sperling - 10 Oct, 2014 - Comments: 0

IP Synopsys rolled out verification IP for mobile PCIe, including built-in M-PHY, for UVM environments. Cadence introduced MIPI SoundWire controller IP, which allows bi-directional digital communication using low gate count and minimal complexity. Deals ARM and TSMC rolled out a road map for 64-bit ARM-based processors at 10nm. The companies said the early pathfinding work is expected t... » read more

Memory VIP
By Neill Mullinger - 09 Oct, 2014 - Comments: 0

As the consumer market, and the mobile segment in particular, continues to demand more features and more performance in their gadgets, the designer community is confronted with myriad challenges of delivering on those demands – not the least of which is verifying compliance of ever-evolving protocols that enable the connection of everything within the system on chip (SoC), and the connection ... » read more

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