Advanced packaging is finally starting to roll out. Now what?
It’s easy to look back on companies or products that missed the market because they were too early. Remember the Eo? The brick-like personal digital assistant that AT&T introduced in 1993 had an antenna that hinted at 4G connectivity. Unfortunately, there was no 4G available at the time, so it was just an extra wire. (Check out the video of the tablet version here.)
Smart watches and smart glasses are still out in front of mass-market adoption. Those markets will likely swell at some point, particularly with the introduction of medical and professional applications and sensors for watches, and augmented reality for glasses. But so far, many people still haven’t discovered reasons why they need to own these devices in the same kinds of volumes as smart phones—or why they should plug them in every night if they do own them.
What’s difficult to see while developing great ideas for future devices is how many pieces of the technology puzzle will be ready or mature enough to propel those technologies forward, and how comfortable users are with those technologies. Companies have been pushing multi-chip packaging since the 1990s as the way of the future. STMicroelectronics, IBM and Intel have been experimenting with 2.5D and 3D packaging approaches for at least the past decade.
Fan-outs and 2.5D are now heading for mainstream. Equipment vendors have developed the necessary tools. All of the big three EDA companies are now firmly on board behind advanced packaging. And most major foundries are offering some form of advanced packaging.
None of this happened overnight, however. Work on advanced packaging began in earnest at the turn of the Millennium when big chipmakers such as IBM and Intel began looking at the impact of continued scaling. The problem at that time wasn’t lithography, because everyone assumed EUV would be available at 28nm or earlier. It was distance and wire thickness. IBM began talking publicly about electron crashes in narrowing wires as early as 2001. RC delay became a subject of concern several years later. And signal paths that could be measured in meters rather than mm began getting some notice.
This was more than a decade ago. GlobalFoundries and TSMC began talking about fan-outs and 2.5D several years ago. But even at the start of 2015, the number of companies willing to jump into this market with commercially available solutions could be counted on one hand. In fact, it wasn’t until the rollout of the second generation of high-bandwidth memory by both SK Hynix and Samsung that the chip market began looking at 2.5D differently, and it wasn’t until companies began experimenting with finFETs and multi-patterning that they began taking fan-outs more seriously.
It’s too early to tell how all of these pieces will fit together in the future. So far, most of the components being used in packages are at the same process node. Initial proponents of 2.5D and 3D expected the real attractiveness of advanced packaging would be the ability to mix and match processors developed at the most advanced geometries with analog components developed at older nodes. That may still happen, but there are always surprises when new technology approaches are rolled out.
At the same time, the march to 7nm is firmly established, and it looks as if 5nm will follow. EUV and multi-beam e-beam are making significant progress, and materials research is well underway to reduce RC delay and to reduce leakage, as in the case of FD-SOI and RF-SOI.
But when these technologies hit the market, and in what form, will depend upon the progress of an ecosystem. That’s true even for large IDMs such as Intel, IBM, and increasingly systems vendors such as Apple. And that raises all sorts of interesting questions about how the technology industry will move forward in the future—and how quickly.