To 7nm And Beyond

GlobalFoundries’ top technologists open up on next-gen FD-SOI, the economics and challenges of 7nm, and what lies ahead.

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Gary Patton, chief technology officer at GlobalFoundries, and Thomas Caulfield, senior vice president and general manager of Fab 8, sat down with Semiconductor Engineering to discuss future directions in technology, including the next rev of FD-SOI, the future of Moore’s Law, and how some very public challenges will likely unfold.

SE: What do you see as the big problem in chips going forward?

Patton: These future nodes are becoming more dominated by middle- and back-end of line resistance/capacitance. But the worst case corner is going to limit what can be achieved from a performance perspective. gary-pattonThere is much more focus on how we control variability. Local layout effects have been a huge issue at 10nm, and the reason people have not achieved the performance gains they were hoping to achieve. Even simple things like random fluctuations can cause problems—one device that is different than the rest of the device and ends up gating performance of the chip. There is a lot in the design technology co-optimization. On 7nm and on 22nm FD, customers have engaged earlier. They’re involved in how we optimize the ground rules to squeeze the most performance, density and power out of the technology.

Caulfield: The big knob for performance in planar devices was strain and strains planning. dr-thomas-caulfieldThe overarching question in performance is what is the ‘celestial’ limit of silicon? Do we need a different material? Do we hit a wall in silicon, not in terms of lithography or feature size, but in terms of performance capability? That’s one of the overarching questions for the industry. How far can silicon take us with all the knobs we’re going to spin?

Patton: It’s not just about performance at any cost. You’re looking for ways to optimize the technology around power and performance at a certain cost point. That’s where 22 FD comes into play.

Caulfield: For a certain class of customers, performance is fair game, so how do you go down the technology performance roadmap? For other guys it’s about power.

Patton: Gartner says that to go from 28nm to 14nm is about a 3X increase in design costs. From 14nm to 7nm, is another 3X. So you’re talking an order of magnitude increase in the cost at 7nm over what it used to cost at 28nm. What’s the cost of that investment. FinFETs are great technology and we’re pushing very hard on that. We have great technology. But the days of one technology fits all are gone. There are people looking for other ways, particularly as these nodes become so expensive. FD-SOI is one. 2.5D and 3D is another opportunity that is coming into play.

SE: We’re certainly hearing more about 2.5D in terms of high-throughput to memory, but there is very little out there on 3D.

Patton: We’ve been shipping 3D with Micron for awhile, too.

SE: One of the issues with 2.5D packaging is the cost of the interposer. Where are we with that?

Patton: We’ve been pushing organic and silicon interposers. We have done work in glass interposers, as well. That has some challenges.

SE: What’s the best choice?

Patton: If you look at some of the industry projections, in 2020 there will still be a large part of the market at 65, 45 and 28nm.

SE: And advanced packaging will allow them to stay there, right?

Patton: Yes. If you have analog/mixed signal content, it doesn’t benefit you to move. If you’re designing analog circuits with finFETs, there is no benefit from going to 7nm because it doesn’t scale. In designing finFETs, because of their discrete nature, you can’t make a 1.6X finFET. It’s either 1X or 2X. Being able to take different kinds of chips with a hybrid nature can be a more cost-effective solution.

SE: Assuming we take process nodes out of the equation, which is really what we’re talking about here, what is required for a really fast chip in the future? Is it microarchitecture, architecture, materials, or is it pushing the process?

Patton: You have to be pushing architecture and design. You have to be focusing on how you can tighten up everything.

SE: What can you do with materials? Are you looking at GaN, SiGe?

Patton: Silicon still has a ways to go. For high-performance logic, there is still a challenge with some of these high-performance materials. We’ve been pushing silicon germanium. We see that as an option for performance enhancement at 7 or 7-plus nanometers. But if you look at these advanced nodes, it’s not so much about strain as parasitic resistances. The resistance getting into the device is the gate. The entire industry is going to cobalt on contacts as a key lever to improve resistance. We have a number of other knobs to improve resistance for back-end of line.

Caulfield: That’s an interesting point, too. Devices used to focus on front-end of line. Now it has shifted to middle-of-line, because that’s the gate. If you don’t solve contact resistance, it doesn’t matter what you do with devices. Once that’s fixed, and you can make that as good as possible, then you have to go back to devices to get the next level of performance. We know silicon will run its course. But at what point do you have to change materials to get to the next level?

Patton: We’re talking 5nm or beyond where we need new transistor materials.

SE: Are we really moving to 5nm? Or will that be too expensive?

Patton: That’s a tricky question because what is 5nm? Somebody could take a 7nm technology, implement it with EUV, and call that 5. Rather than talking about novel materials, you may be talking about new device structures like silicon nanowires or vertical devices. We have a number of projects going in Albany on this.

SE: One of those is a complementary approach where, in addition to the gate-all-around FET there is a complementary idea where you have one on top of another, right?

Patton: Yes, and IMEC has published material on that. You have the nanowire stack, where one is the nFET and one is the pFET. All that means more complexity.

Caulfield: And more mask steps. The memory guys get away with vertical because they’re just putting a bunch of films in one step and etching. It’s an elegant way of getting to a feature size in the vertical dimension. But when you need to build transistors on top of each other, you’re trading off the complexity of fine patterning with many more mask steps.

Patton: There are projections that 7nm is going to be in the 80-mask range. People think about EUV for scaling, but at least in the initial phase the cycle-time improvement will be a great benefit. To be able to go from 80-plus masks down to 60-plus masks would be a huge benefit. Add to that the defect density benefit, because you’re not depositing and etching and running all these process steps that add defects to the wafers.

Caulfield: Even with 14/16nm technologies, the number of mask steps are in the low 60s. You can do some of the lower-order thin wire quad patterning, cut masks steps out, and all of a sudden you’re doing the same number of mask steps at 7nm.

SE: So you’re trying to stay level with where you are at 14nm?

Caulfield: Yes. Even in the 60s is tremendous complexity. Keeping wafers in the fab doesn’t improve yield. The opportunity for bad things to happen increases. That’s the value in 7nm. The complexity reduction would be huge.

Patton: We announced an advanced patterning center with New York State last year. We’re putting our second EUV tool in there to increase the ability to do research on EUV. We’re running wafers back and forth between Malta and Albany. For device learning, you don’t really care if some of the back-end levels are done with EUV or immersion. You get your device results out as quickly as possible, and at the same time we get learning on EUV.

SE: So if your costs are going up and your performance is not increasing significantly, what do you get out of moving to the next node?

Patton: 7nm will have a reasonable performance increase over 14nm, because there are a lot of things we’re doing in the technology. 10nm was focused on the wrong things for improvement. It focused on strain, which wasn’t really a big lever. It missed things like local layout effects. We’re really focused (at 7nm) on how we improve the parasitics of the transistors so we get all the performance out. We’ve done a pretty extensive calculation across several process technology nodes and our device data at 7nm is right where we projected. We have a whole bunch of elements that we’re implementing that will get us to our performance target. 7nm has a pretty aggressive scaling factor. It’s a 64% reduction in area to compensate for the fact that you have additional masks. If you look back, 20nm was the worst place to park. If you have to introduce double or triple patterning, you want to scale it beyond that to get some advantage. But that was parked right where you needed double patterning and you didn’t really get a lot. If we’re driving things to a density where we need triple or quadruple patterning, we need to get a return for that.

SE: Do you get that same kind of benefit from 5nm?

Patton: It’s too early to tell, but it looks challenging. That may mean it takes longer to get to a true 5nm. If it has to have EUV, and it has to have new device structures, it will take a long time. 7nm will be a long node in my view. There will be performance tweaks on it.

Caulfield: But here is what the industry is learning: If a design is going to cost $300 million to $500 million, it better have real value. With 20nm, there were two high-volume chips, but the rest of the industry saw that as a failure. Every node will be defined. With 7nm, if you shrink 65% you can get a real cost savings. Complexity goes up, so maybe you don’t get the full savings, but you get a portion of that, and you get performance. We believe 10nm will be a few companies looking for performance to hit a market, and everyone else will wait for 7nm.

Patton: 20nm was a misstep in my opinion. It was improved with a 14/16nm finFET, but it was really a 20nm process. 10nm was another misstep. There is not a huge value proposition in terms of performance. With local layout effects, they’re getting very little performance improvement. There is a power benefit, but very little in terms of performance or cost. If people rush to 5nm, it could be a repeat of 10. If we take our time and really define the node, then it could be a good technology node.

SE: How serious is the current leakage problem after 14nm? We had an improvement with the first generation of finFETs, but that goes down at each successive node.

Patton: It’s something we still need to focus on. New technologies could mitigate that. The jury is still out on where we go with 5nm.

Caulfield: We’re getting to the point where you need to look at alternative technologies. With FD-SOI with back-biasing allow you to overcome leakage and lower voltage. It depends on what’s important for you.

Patton: We have a next generation FD-SOI technology we’re developing.

SE: Wasn’t that 10nm?

Patton: It’s probably somewhere in the 12nm to 14nm range. This is a cost-focused play. Going to 7nm if you’re not in the IT space doesn’t make sense.

SE: The number of question marks you have at each new node—process, equipment, new fabs—are now measured in enormous investments. How do you deal with that?

Patton: One of the key focal points for us is early engagement with design customers. We have several customers we have been working with on 7nm, and we have been for quite a while. For the past nine months we have been having weekly meetings with these customers—working through the definition of the technology, how do we optimize their product, what changes can we make to achieve the best tradeoff between cost, performance and power? And then putting device structures on our test sites so we can understand that and validate it, so we can get feedback and tune it. This engagement is critical.

Caulfield: With 7nm, we have a very diverse customer set. Having content so they can get an early look means they are not just kicking tires. They’re spending real engineering effort to create IP for the next generation. They’re betting on it. Early engagement is the only way to make sure this stuff comes together. They can’t be a fast follower. To do leading-edge stuff, they have to be in very early because of these design interaction kinds of things. It’s great to know your customers need a product refresh, but how do you stay competitive, especially with the mobile guys who look at who’s doing what? We can fill the capacity because there are enough people who require that next generation of technology and the benefits that technology will bring to them. The model, though, of how you make this all sustainable keeps coming back to scale. The volumes are not necessarily higher than they were in the past, and consolidation has changed the industry. But there are a few people who can still do it, and they can do it with economic scale.

SE: We’ve been here before in terms of, ‘What are we going to be using all of that processing power or memory for?’ Is this different?

Patton: The issue is economics—the cost and return on doing a 5nm chip. There won’t be a return for everybody. That’s why we placed a bet on 22FD and our next FD road map. We think that people will look at the cost of doing design for these fast nodes. There are a ton of people still back at 40nm and 28nm who haven’t made a decision about where they’re going to go. They could go with finFETs, which do offer good performance. But they’re locking themselves into something with high design costs and high complexity. Or they can take the FD-SOI route. That’s much easier to design in at a lower cost point. You can do forward and reverse body bias on transistors. You can get to very low voltages. We’ve demonstrated 0.4 volts. We’ve also demonstrated very low leakage. We can get down to 1 picoamp per micron.

SE: Is that the same if you move from 22 FD-SOI to 12nm or 14nm FD-SOI?

Patton: We’ll definitely have increased performance with similar leakage. We also expect to get a good play with RF devices. That’s another thing with FD—integrating logic and RF on a single chip. With finFETs, you can get into the 200 GHz range for an RF device, but with FD-SOI we’re way up into the 300 GHz range. It’s ideally suited for the RF space.

Caulfield: The last part of that equation is packaging. The problem with multi-chip module packaging was that it was way ahead of the market needs. It was always cheaper to integrate at the die level than at the package level. When the economics turn on that, packaging will become the next knob we turn. 2.5D/3D packaging may be how Moore’s Law scales, but in a very different way.

SE: When will we see economies of scale?

Patton: If you look at C4 (controlled collapse chip connection, aka flip chip), that came out as a boutique technology. It was expensive. But over time, people worked on reducing the cost. Now it’s prevalent.

Caufield: You can’t buy a package today that doesn’t have a ball grid array of some sort.

SE: What worries you about technology in the short-term and mid-term?

Patton: We’ve talked about some of it. One is the economics of making investments at advanced nodes and getting a return. There are fewer and fewer players. Part of that is consolidation. On top of that, the number of customers willing to make that kind of investment is shrinking. But that’s why we have focused on a very diversified portfolio. With the IBM acquisition, we acquired a really advanced team. That enabled us to develop our own 7nm technology as well as RF technology. That’s going to be huge with IoT. IBM was No. 1 in the RF space. RF and mixed signal is a huge area of investment for us now. It’s going to benefit all the fabs. Burlington (Vermont) is the hub. We have RF in Singapore. We’re bringing RF into our 22FD technology in Dresden. ASICs is another one. A lot of people are looking for a low-cost way to do these designs and they want more of a complete solution. IBM was No. 1 in ASICs in the communication space. There also are lots of wins for 14nm, and we’re already getting quotes for ASICs at 7nm.

SE: Are those standalone chips or will they become platforms?

Caulfield: There are different plays for that. There will be platforms, which are traditional. There’s also a piece of this where as a foundry I can help with a couple pieces of IP because the volume doesn’t make sense. We didn’t buy the IP portfolio to be in the standalone IP business. It’s part of a portfolio. We want to find a way to leverage it broadly.

SE: We came up with one consolidated IP-ASIC roadmap. There’s a big chunk of IP that is redundant, so we bore the cost and allowed them to develop new IP. We also partnered with companies like Invecas. They’ve been instrumental in developing IP at 20nm, and they’ve been instrumental at 7nm.

Caulfield: But to go back to your earlier question, there are a couple things that keep us up at night. One is the sustainability of the business model. The other is technology. If you look at the industry starting at 20nm, two of the three nodes failed to deliver. That never happened before. I’m pretty confident we will get the fidelity in the feature side. The wild card is performance. We’re confident we’re going to get there, but we haven’t proven that yet. The industry is struggling with that. We really win big if we can do it and the other guys can’t.

SE: Do you get a performance boost moving to FD-SOI at 12/14nm?

Patton: There will be a basic device performance improvement. But we also will be introducing a much richer implementation of the forward and reverse body bias. That will give you significant improvement, as well. And then, RF devices will be improved, as well.

SE: Can one company do this anymore, or is it part of an ecosystem?

Caulfield: We look at is as a virtual IDM. That name was ahead of its time, but we’re heading to that.

Patton: It is becoming an ecosystem, too. When we introduced 22FD we engaged on the EDA side with Cadence, Synopsys and Mentor Graphics. We also engaged with IP partners like Invecas and ARM. You need to build an extensive ecosystem if you want people to get the most out of the technology.

Related Stories
10nm Versus 7nm
The economics and benefits of moving to the next process node are not so obvious anymore.
Pain Points at 7nm
More rules, variation and data expected as IP and tools begin early qualification process.
7nm Lithography Choices
Four possible scenarios for patterning the next generation of chips.



  • Byungchun Yang

    Dear Ed, Gary and Tom,

    Thank you for the opinions and views you shared with us. One thing I would like to mention is that not many are tolerant to new approaches, saying they have to do something to solve the big problems they have been suffering for many years already! As you said, BEOL resistance is a huge concern, and increasing via resistance is one of the big reasons why we have this problem. Please remember that We cannot remove the resistance increase due to miniaturization since that is the true nature of the Cu material we are using! let’s forget about it for good! However, we can deal with the via resistance problem for which you can benefit much if you could resolve it when others cannot. The via resistance problem is due to the current damascene process in which not much via bottom clean is allowed due to Cu contamination to PLK materials.

    BC Yang

    • Byungchun Yang

      And, except Intel, not many people are interested in this kind of discussion any more. I am sorry but that is what I perceive recently. They have been repeatedly talking about the same concerns, and did nothing to remove those. The third damascene process I mentioned has been ardently supported by IBM and Novellus in the past. It failed due to its extreme simplification of process flow, and now they don’t even take a look at my improved version, using AMAT’s BKM damascene process that has a big flaw I mentioned earlier.

  • memister

    Samsung also noted 20, 14 and 10nm all had ~60 masks just like 7nm EUV, but with some of the ~60 193i masks replaced by EUV it is actually slower overall than 10nm and thus more costly.

  • Sang Kim

    Sang Kim
    28nm bulk technology is in mass production for several years by major semiconductor companies but not 28nm FD-SOI yet today. Why FD-SOI is not manufactured even at 28nm unlike 28nm bulk? If FD-SOI is not manufacture-able at 28nm, it will not be manufactured at any node below 28nm.
    IBM created the international SOI consortium about a decade ago and then faded away. One of the biggest issues with 28nm FD-SOI is the hot carrier reliability. It is because unlike 28nm bulk the 28nn FD-SOI doesn’t have the LDD(Lightly Doped Drain) to minimize hot carrier generation. Also, the hot carrier reliability will become worse with scaling. Therefore, unless the hot carrier issue is resolved at 28nm, FDSOI can’t be realized.
    Furthermore, what happens when hot carrier are generated near the drain in normal FDSOI operation? Electrons go to the positively biased drain with no harm but where the holes to go? The holes can’t go to the substrate because of the very thin burred SOI layer below. Therefore, some holes may become trapped at the burred thin oxide layer causing Vt shift but vast majority of holes drifts through the un-doped SOI channel toward the N+source, resulting in device failure, thus ending 28nm FDSOI.
    Also, how thin SOI thickness is required for 14nm that is manufactured by Intel over three years? About 4nm! I doubt 4nm can be deposited uniformly and reliably over 12″ wafers at the manufacturing line. If not manufacture-able, FDSOI is not scale-able.