With voltages possibly below 0.5 volts, TFETs are a serious contender for ultra low-power applications at 5nm.
Traditional CMOS scaling will continue for the foreseeable future, possibly to the 5nm node and perhaps beyond, according to many chipmakers.
In fact, chipmakers already are plotting out a path toward the 5nm node, but needless to say, the industry faces a multitude of challenges along the road. Presently, the leading transistor candidates for 5nm are the usual suspects—III-V finFETs; gate-all-around; and nanowires. But suddenly, momentum has started building for another emerging candidate: the tunnel field-effect transistor (TFET).
CEA-Leti, IBM, Imec, Intel and others are aggressively working on TFETs, and for good reason. Currently aimed for 5nm, TFETs are steep sub-threshold slope transistors that can scale the supply voltages below 1 volt, and possibly as low as sub-0.5 volts. The TFET is similar to today’s MOSFETs, but the TFET is actually a gated-diode that makes use of an electron tunneling technology. In theory, TFETs could switch on and off at lower voltages than current and future finFETs.
“TFET is a hot field,” said Aaron Thean, director of the logic program at Imec. “There is a grand challenge of how to make a switch that could beat the 60-millivolt per decade swing. Tunnel FETs can break that barrier. In principal, TFETs can actually go below the 60-millivolt per decade swing at room temperature. That’s why there is a lot of interest.”
In the future, TFETs could be ideal for low-power applications, including one emerging field, near-threshold computing. “A lot of people are looking at near-threshold computing as a way to address the power from a system side,” Thean said. “The idea is to crank down the voltage. We’re talking about 0.5-volt and below. TFETs could be a major contender in this space.”
Putting TFETs into production is easier said than done. Like the futuristic finFETs, TFETs may require III-V materials, nanowires and other complex technologies. “These devices are in the right direction for the industry, but the functional demonstration isn’t there yet,” said Adam Brand, senior director of the Transistor Technology Group at Applied Materials. “There are still a number of problems to solve to make this device work.”
For years, TFETs were mainly the subject of technical papers and research at the universities. In the lab, for example, Pennsylvania State University and the University of Notre Dame recently demonstrated staggered and broken gap tunnel junctions in InGaAs/GaAsSb TFETs.
Then, the industry began to get serious about TFETs in 2010, when Europe launched the so-called Steeper project. The program, which involves the development of TFETs, includes CEA-Leti, EPFL, GlobalFoundries, IBM, Intel and others.
In the last two years, IBM and Intel demonstrated their first TFETs in the lab. And at the upcoming IEEE International Electron Devices Meeting (IEDM) in December, Imec, Intel and others are expected to present their latest results on TFETs. Imec will describe a vertical TFET, while Intel will roll out a new device–the resonant-TFET (R-TFET).
TFETs could appear in 2D and 3D configurations. They could be based on bulk CMOS or silicon-on-insulator (SOI) technology. And in theory, TFETs could solve a major problem. Generally, today’s MOSFETs, which operate by emission over an energy barrier, are limited to 60-mV/decade, making them difficult to scale below 0.5 volts.
The TFET is a PiN-gated diode that operates in reverse bias. TFETs make use of band-to-band tunneling of electrons through a barrier, as opposed to flowing over a barrier as in MOSFETs.
TFETs have some advantages, and disadvantages, compared to finFETs. “Today, finFETs are driving a lot of current. They are doing that very well,” said Imec’s Thean. “If you look at TFETs, they don’t put out a lot of current. In fact, they are short on current. But when you start lowering the supply voltage, and we are talking about sub-0.5 volts, there is a regime where the TFET will win out. Then, the finFET and nanowire start to drop out of the race, because the sub-threshold swing is not steep enough.”
It’s hard to predict, but the industry could see various chip architectures in production by the 5nm node, such as 3D devices, III-V finFETs, gate-all-around and perhaps the TFET.
All of the futuristic technologies have several challenges. “Gate-all-around with a vertical pitch looks very interesting. But if we talk to designers (about gate-all-around), they will go crazy. They don’t need to know how to design with all of these features,” said Jo De Boeck, chief technology officer at Imec. “The (III-V finFETs) are still on the roadmap, but they are not manufacturable yet. The promises in terms of performance have yet to be seen.”
De Boeck said TFETs have some integration issues, but they look promising. “TFETs will find its place, as we see it, in the ultra-low power segment,” he said.
Intel, for one, has a keen interest in the technology. Two years ago, Intel described an InGaAs TFET with sub-60mV/decade switching. “There are several types of TFETs,” said Michael Mayberry, vice president of the Technology and Manufacturing Group and director of components research at Intel. “A TFET is a more straightforward technology to implement, but there are still a lot of challenges.”
At the upcoming IEDM event, Intel will describe a double-gated and heterojunction TFET with nanowires at 9nm. In addition, Intel will describe the R-TFET, a device that enables sub-9nm gate-lengths. The R-TFET is said to have a 25mV/decade with a Vdd=0.27V.
Intel’s TFETs are based on bulk CMOS. In contrast, CEA-Leti has described a TFET based on a fully depleted SOI (FDSOI) process flow, featuring a high-k/metal-gate scheme and strained silicon-germanium. Still others are looking at vertical or 3D TFETs. Last year, IBM demonstrated an InAs-Si vertical heterojunction tunnel diodes with record high currents and TFETs with a slope of 150mV/decade.
Meanwhile, at the upcoming IEDM, Imec will describe a heterojunction vertical TFET or VTFET. “We have demonstrated a germanium source heterojunction device or a germanium-source-on-silicon,” said Imec’s Thean. “And it’s vertical. Why is it vertical? We envision by the 5nm node and beyond, there will not be much space to do regular layouts. Going vertical gives us advantages. We can selectively convert any of the silicon pillars and grow different types of devices using this method selectively.”
Don’t expect the technology in the near term. “TFET is targeted for 5nm, at least on Imec’s roadmap,” he said. “Will it be ready for the 7nm node? The outlook is not bright, because there are a lot of fundamental issues.”
Indeed, there are several challenges to get TFETs into production, said Alan Seabaugh, a professor of electrical engineering at the University of Notre Dame, which has been working on TFETs for several years. “There are new materials. And you don’t have much experience in the gate dielectrics for these systems. You also have to get both n and p channels working,” Seabaugh said.
While the industry is still wrestling with these challenges, researchers are now looking beyond the current round of TFETs. “The universities are now looking at what happens after III-V TFETs,” Seabaugh said. “If you really think what you want in a steep device, it may not be a semiconductor material as we know it. These are some of the 2D or single-atomic layer materials, like graphene or some of the di-chalcogenides, such as molybdenum disulfide and molybdenum tellurite. Ultimately, those materials may be options for TFETs.”
The options, of course, depend on a given application. “You have to think about 20 years or 25 years out,” he said. “What do we want to do? We want technologies that can really lower the voltage down, maybe low enough to do computing with scavenger generation. We are not going to do that without some big breakthroughs in the device.”