Interleaved transistors; neuromorphic photonic modeling; re-using verification for security; 3D-IC reliability; memory bandwidth regulation.
Find all technical papers in Semiconductor Engineering’s library.
| Technical Paper | Research Organizations |
|---|---|
| Efficacy Of Transistor Interleaving In DICE Flip-Flops At A 22 Nm FD SOI Technology Node | University of Saskatchewan |
| Neuromorphic Photonic Circuit Modeling In Verilog-A | Queen’s University, University of British Columbia, Princeton University |
| Reusing Verification Assertions As Security Checkers For Hardware Trojan Detection | Centre for Hardware Security Tallinn University of Technology (TalTech), Estonia |
| Artificial Intelligence Deep Learning For 3D IC Reliability Prediction | National Yang Ming Chiao Tung University, National Center for High-Performance Computing (Taiwan), Tunghai University, MA-Tek Inc, and UCLA |
| Real-Time Instruction-Level Verification Of Remote IoT/CPS Devices Via Side Channels | University of Florida |
| Tile-Based Massively Scalable MIMO And Phased Arrays For 5G/B5G-Enabled Smart Skins And Reconfigurable Intelligent Surfaces | Georgia Tech |
| A Novel Power-Saving Reversing Camera System With Artificial Intelligence Object Detection | National Yang Ming Chiao Tung University, Avisonic Technology Corp |
| Memory Bandwidth Regulation On Hybrid NVM/DRAM Platforms | Shanghai Jiao Tong University |
| FLODAM: Cross-Layer Reliability Analysis Flow For Complex Hardware Designs | Univ. Rennes, IRISA, ONERA, DGA, Temento |
| Van Der Waals Semiconductor Empowered Vertical Color Sensor | Georgia State, Clemson University, Oak Ridge National Lab (ORNL) |
| Stress Tensor Mesostructures For Deterministic Figuring Of Thin Substrates | MIT and University of Arizona, funded by NASA |
| Hardware-Supported Patching Of Security Bugs In Hardware IP Blocks | Duke University, University of Calgary, NYU & Intel |
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