A New Dawn For IP

The IP industry is changing again. The concept started as build once, use everywhere, but today it is more like architect once, customize everywhere.

Few designs can afford sub-optimal IP for their application. The need for customized IP is driven by both leading-edge designs and the trailing markets, although for different reasons. While this customization is causing IP companies to transform their practices, it makes having access to domain expertise even more valuable.

The original justification for IP remains the same. “Partners often take the decision to add custom IP only when it gives them effective ways to differentiate in the market,” says Thomas Ensergueix, senior director in the Automotive and IoT Line of Business at Arm. “A big factor to consider when developing custom IP is balancing the cost of the investment in development and, most importantly, validation against the benefits of the overall system performance. Large customers often rely on thoroughly validated off-the-shelf IP for much of the design, focusing their effort on a few areas where they can have the biggest impact, based on their expertise.”

A design that has been used in silicon many times is likely to be of higher quality. “The cost of manufacturing, especially designs in 7nm or 5nm, has become so expensive that customers do not want to take the risk,” says Rishi Chugh, senior product management group director for the IP group of Cadence. “Not only do they get the leverage of the IP, but also of the toolsets to integrate these complex IP into their SoCs. The levels of complications have increased, and the risk is not worth taking.”

But for some companies, optimization of the system means optimization of its components. “The entire industry has realized that general-purpose compute and general-purpose IP is no longer able to provide the most optimal design, be it in performance, power or area,” says Mo Faisal, president and CEO for Movellus. “This is what drove Apple to buy their own processor company and now they can optimize the processor along with their software. It is that co-optimization and co-design that has become necessary. Now we see companies like Facebook, Google and Amazon all doing their own silicon. First, they realized that hardware and software had to be co-optimized and co-designed. Now, within the SoCs, that is the next level. The system has to be co-designed and co-optimized with the IP. If you don’t do that you end up leaving a lot of performance and power on the table.”

It might appear as if the demands of the IP user and the needs of the IP supplier are different. “There is a real pressure coming all the way down the stack to the IP providers who are trying to produce a building block that can be incorporated into a lot of devices,” says Andrew Grant, senior product director at Imagination Technologies. “We often find that within an engagement, where the evaluation period could go on for six or nine months, that their demands change throughout the process as they learn about their end market. So there is a lot more customization required to fit a particular market, which does make life more difficult for IP providers.”

Today, more factors are in play than ever before. “One size fits all is still true, but that one size needs to be able to be customized to meet their needs,” says Mick Posner, senior director for High Performance Computing IP at Synopsys. “The evolution has been in the space of power, performance and area (PPA), but also in cost, which is outside of the IP but plays into it. We are seeing increased usage of cheaper packages, and we need to account for that in the IP. If we tried to account for that in an off-the-shelf manner, the additional cost to build the IP really breaks the ‘build once, sell many’ to recoup your investment. It extends outside the chip as well to the components that are being used, such as the use of cheap reference clocks, the use of low-cost PCBs — those are pushing the customization of IP in a different manner.”

As Moore’s Law slows for many, it creates a new dynamic. “In general, the productivity of the semiconductor industry has gone up thanks to the capability of EDA tools and the explosion of engineers in India and China,” says Movellus’ Faisal. “This is resulting in more people doing more complex SoCs, and some people have the luxury of putting things together in a customized manner. They can buy a standard IP and customize it, or they can hire a company that will customize it for them. Another reason is that their risk profile has changed , especially those in older nodes. This makes them open to quick customizations because they are likely to focus on one market vertical. The process node is also becoming highly customized. There are five or six flavors for every process node. That puts additional pressure on the IP ecosystem.”

Market verticals
Until recently, it was the mobile phone industry that had been the driver for many of the most advanced technologies and methodologies. Today, several other sectors have risen to a level of prominence where IP vendors are taking notice.

“Customization of IP is happening based on the segmentation of the product,” says Cadence’s Chugh. “Consider PCIe. The same design is used for hyper-scalers, for infrastructure and for datacenter. That is one set of IP. Then there is the same PCIe, which when used in automotive markets requires a level of customization because you have to get that qualified, you have to meet standards for automotive and the test coverage is different. Customization is necessary on the base design. Similarly, PCIe for storage, especially when used for SSDs, has stringent latency requirements that are over and above the PCI protocol. You can call it customization, or you can call it segment-specific requirements. The IP does have to be fine tuned for those applications.”

The demands of automotive are having significant impacts on the markets. “In automotive, EMI analysis is important,” says Farzad Zarrinfar, managing director of IP at Mentor, a Siemens Business. “They want to see the electromigration characteristics of memory for a different range of temperature and at the specific frequency where it is intended to operate. They need to know the impact of EMI after 5 years or 10 years. Nobody has needed this analysis in the past. They may also need to look at inductive switching and make sure there is no disturbance to memory. So I may need to put the memory in a deep N-well technology. We can put the same IP inside the deep N-well to protect it from disturbance.”

Fig 1: Protecting sensitive logic in a deep N-Well. Source: Mentor, a Siemens Business

Synopsys has organized its IP group by end-market segments. “The reason for having a segment organization is because we are pulled in many different directions,” says Posner. “While I tend to the needs of high-performance computing (HPC), another segment is more consumer-based, while automotive also has its own segment driver. This pulls the IP in different directions. Our IP is developed with customization in mind because of this, knowing that to meet most of the market demands we need to have flexibility. We need to be agile to catch these early adopters. Having segments set up to foresee the market needs is essential to our success.”

In many cases, it requires significant analysis at the system level to know what customizations are required. “Custom optimizations are very often driven by specific workloads and use cases that are well understood only at the system-level,” says Arm’s Ensergueix. “As an example, a custom SoC for smart cameras might have face recognition as a primary requirement, thus the architecture must take that in consideration. Furthermore, through system-level modelling partners can simulate the performance of specific workloads on different combinations of IP and configurations to identify the best solution.”

“If you can find a sweet spot that hits multiple sectors, then you have a winner,” says Imagination’s Grant. “That is different from the way the market worked five years ago, and that trend will accelerate. Everything we are doing has to be very flexible. So when you think about the source code, you are thinking about what can be optimized for as many markets as possible and how can I contain that information going forward. The software to make all of that work optimally often can take longer to produce than a hardware IP core. You are always looking at how to get the maximum result with the minimum customization while at the same time making sure that what we are doing does fit a market’s needs.”

This means that IP architecture is becoming more important. “If you do not have the right knobs when you architect the IP then it becomes a nightmare for the organization because the turnaround time will increase and it is not a scalable model,” adds Chugh. “If the right variables have been built in, then you can always satisfy the needs of customization.”

Closed systems
Standards often are created to cover the whole industry, but not all segments need the whole standard.

“PCIe within HPC will utilize all of the capabilities and modes,” says Faisal. “But if you talk about mobile, or IoT or edge, your PCIe appears bloated. You don’t want all of the modes, you don’t want all of the ranges. You may only be communicating at 5 Gb/s instead of 16 Gb/s. You have a choice — do you buy a standard PCIe product or do you realize that if you have the resources or a vendor who is willing to customize it for you, you will end up saving a lot of power and area?”

But this is not the only reason why an increasing number of systems are demanding customized IP. “In some deployments today, especially those coming from the hyperscalers, they are closed-box,” says Chugh. “They don’t care about external vendors. They only have to worry about what is happening within the data center, and they want the best within that spectrum.”

This kind of customization is expanding as new markets emerge. “We call that protocol extension, just to be nice,” says Posner. “This happens especially in emerging areas, such as machine learning and AI, low-latency networking, multi-die NICs. We see the need for the IP to be customized to be differentiated. A common example is the reduction in latency. You could view these as PPA optimizations, but these are typically extensions that go outside of the protocol, and this is only possible because they are targeting a closed environment. It could be for a die-to-die interface where they may be utilizing what they see as an off-the-shelf Ethernet PHY, but it has a specific latency requirement that is not part of the Ethernet specification. It is tailored for that need and can only be used within that system.”

System analysis
IP no longer can be designed in isolation. Some optimizations are necessary between system components. “Things like PCIe, or DDR and the DMA structure, have to be tuned based on the ISA standards,” says Chugh. “If you don’t do that, performance and latency suffer. One processor vendor will say that for PCIe, they want ‘this’ to happen, or another will say what they need. A third will say, ‘My processor has these unique features, and make sure when you design the PCIe it has these levels of interrupts or these virtual flows so that I can take advantage of them rather than relying on the kernel.'”

This is leading some IP vendors to look at larger subsystems. “The race to optimize individual IP in isolation will become less relevant, and the industry will need to make a shift toward thinking about the entire system and optimize for specific use cases,” says Ensergueix. “In this context, system-level optimizations happen across multiple IPs, including software and tools. For example, Arm aims to architect the next generation of devices where CPU, GPU, NPU, interconnect and system IP are all designed from the ground up and optimized with software and tools as an integrated solution. By focusing on specific use-cases, this approach will deliver better system-level performance compared with an individual IP approach.”

Optimization is possible all the way from the system-level down to the process level. “System companies want extremely customized and specialized systems, and they want to take that all the way down to the transistor level — even the process level,” says Faisal. “There are foundries that will customize the process for a vertical, such as edge AI. If you use general-purpose IP, you end up throwing away the time and effort that you have spent doing optimization at the system level.”

And this can have an impact on all parts of the chip. “Over 50% of a chip is memory,” says Mentor’s Zarrinfar. “For analysis, you have to utilize different abstraction layers. The highest level enables you to look at the design and integrate software. You can run the application and get some ideas about what is required. As you come down to lower levels, such as the SoC level, you can run a what-if analysis at RTL or SystemC level. It will provide power, speed and area numbers. You can define multiple clock domains and do what-if analysis. The days when they want a .lib in three different corners are gone. They are asking for 100 different PVT corners and want to see the timing and power across different power domains. When they have what they want, then we can ship the GDSII of that IP.”

This may require some new flows and tools. “New flows are required that bridge the gap between IP and the system-design domain,” says Benjamin Prautsch, group manager for mixed-signal automation at Fraunhofer IIS’ Engineering of Adaptive Systems Division. “Much of this is still considered to be research, although there are some interesting developments in this area. Today, optimization tends to be by component selection, which could likely cause non-optimal overall design performance.”

Conclusion
In 1996, the Virtual Silicon Interface Alliance (VSIA) was formed to help bring structure to the emerging IP space. While it met with some success, it never could keep up with the changing demands being placed on IP and on the companies developing and delivering it. There has never been a time when the demands of the IP industry have not been changing.

What the industry initially got wrong was that it considered it to be the code for the IP that was important, when in fact what was happening was knowledge specialization. A dedicated team that was focused on a particular piece of a design could understand that better than someone trying to design a complete system. The dedicated team had more experience and they could use that to produce better implementations.

Today, knowledge specialization is becoming even more important. IP teams are having to work closely with systems’ companies to produce the pieces of IP that meet their increasingly individual needs. IP vendors are meeting this challenge through experience and by increasing levels of technology that can help them perform these customizations efficiently and effectively.

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