Advanced Packaging Drives Test And Metrology Innovations

Advanced packaging has become a focal point for innovation as the semiconductor industry continues to push for increased transistor density and better performance. But the pace of change is accelerating, making it harder for the entire ecosystem to keep up with those changes.

In the past, major developments were roughly on an 18-month to 2-year cadence. Today, this is happening every few months. Moreover, it’s now accompanied by a diversification of package types, which is driving up the cost of equipment and testing and forcing the industry to diversify into packaging-specific silos.

“There are so many different solutions, and different manufacturers are migrating to what works for them,” says John Hoffman, computer vision engineering manager at Nordson Test & Inspection. “We’re seeing more and more variation in processes and packages tailored to unique needs, creating a new landscape of specialized packaging paths.”

Metrology is adapting to meet these varied demands, integrating techniques tailored to the complex structures of each packaging type. Technologies such as X-ray fluorescence (XRF), atomic force microscopy (AFM), ellipsometry, and white-light interferometry provide engineers with unprecedented precision and capabilities, but they also have their limitations.

“The requirements for precision are getting tighter. We’re measuring thinner films and at smaller scales,” says Sean Hand, senior staff applications scientist at Bruker. “And every new package demands something different, whether it’s tackling metal oxide thickness for hybrid bonding or navigating shifts in material properties.”

Signal integrity and thermal testing
As device complexity and demand for high-frequency performance continue to grow, ensuring signal integrity and managing heat have become more challenging for advanced packaging. This dual challenge is pronounced in high-performance computing (HPC) applications, particularly with the increased focus on AI, where signal and thermal density create unique obstacles in design and testing. Engineers now must contend with packages containing hundreds or even thousands of signals, each requiring an interference-free path to maintain data fidelity and prevent performance degradation. Maintaining clean signal transmission and managing thermal stress are vital as these packages are pushed to their operational limits.

“The challenge with high-density and high-data-rate packages is ensuring that signal paths remain clean even as we push higher data rates and more complex interconnects,” says Jeorge Hurtarte, senior director of product marketing in the Semiconductor Test Group at Teradyne. “It’s essential to maintain interference-free transmission paths for reliability, especially with HPC devices operating at such high data rates.”

Signal integrity has become a growing concern in this environment. With high-speed, high-frequency signals, the likelihood of signal degradation, interference, and reflection increases, making precise testing methods essential to detect and mitigate these issues.

“High-speed testing requires a carefully designed signal path at high speeds (224 Gbps or 80 GHz bandwidth today, and rising) to the device under test (DUT),” says Dave Armstrong, principal test strategist at Advantest. “Doing this for a large number of signals for the newest advanced packages is becoming increasingly difficult.”

Achieving signal integrity isn’t solely about high-speed pathways. It also involves precise calibration and advanced error correction to compensate for potential losses and ensure measurement accuracy. Engineers face the added complexity of minimizing data noise in multi-layer and high-density packages.

“As the node sizes shrink and pitch sizes get smaller, inspection speed slows while accuracy demands increase,” says Nordson’s Hoffman. “If frequencies aren’t properly managed, you’ll see noise and interference creeping in, which impacts inspection times and the data you’re able to capture accurately.”

It’s becoming necessary to adapt testing strategies, as requirements for high-frequency and high-density devices continue to evolve. Traditional general-purpose I/O (GPIO) testing methods are becoming less effective as more designs rely on high-frequency functional interfaces, which introduce additional challenges in isolation and signal fidelity. Engineers now face the task of testing these high-frequency interfaces directly to ensure structural integrity and minimize interference.

This shift highlights the need for specialized approaches in high-frequency testing to meet the requirements of today’s advanced semiconductor devices. “The use of standard GPIOs for testing has declined sharply,” notes Vidya Neerkundar, product manager for Tessent at Siemens EDA. “For testing purposes, high-frequency functional interfaces must be used, and we need proper isolation from other interfaces on the chip. Testing these interfaces independently to ensure structural integrity, regardless of their functional design, is now essential.”

Thermal management, another critical aspect in testing advanced packaging, likewise has seen increased complexity. The intense current demands of today’s high-density packages lead to substantial heat output, which can cause warping, failure, or performance degradation if left unchecked. Efficient heat management systems have thus become indispensable, particularly for packages designed for high-frequency applications where thermal stress could disrupt signal fidelity or cause material deformation.

“Delivering the current required by large HPC packages has become a true art,” says Advantest’s Armstrong, emphasizing the importance of a carefully designed power distribution network with precise thermal design. “A robust heat removal system is necessary to prevent parts from overheating, especially as some devices consume over 2 kW. Once the thermal test setup is solid, the task shifts to confirming the power dissipation of the various cores on the DUT in order to identify the best way to ‘harvest’ a device while maximizing profit and reliability. This requires careful test development, data gathering, and analysis.”

Advanced thermal management solutions go beyond just preventing overheating. They also focus on reliable performance that is sustained over prolonged periods. These systems require such innovations as precise heat dissipation pathways and robust materials that can handle thermal cycling without wear.

“Every time we try to increase efficiency, we’re adding layers of complexity in both the thermal design and the inspection criteria,” adds Hoffman. “Testing in this realm requires tools that adapt to a variety of thermal profiles.”

As signal integrity and thermal performance remain at the forefront of advanced package design, these dual aspects continue to drive innovation, highlighting the need for tailored solutions that address the specific demands of each high-density package type.

ATE vs. SLT
As advanced packaging technology continues to evolve, a dual approach of implementing ATE for rapid, high-volume testing at wafer and packaged levels, followed by SLT for system-level evaluation, is becoming the new standard in advanced packaging. That combination ensures devices are both functionally sound and able to perform under complex, real-world conditions.

“ATE serves as a fundamental tool for screening defects and validating basic functionality,” says Hurtarte. “But as we move into 3D and heterogeneous integrations, SLT allows us to verify how these devices will behave in real-world conditions, capturing performance characteristics that ATE alone cannot provide. Furthermore, with both ATE and SLT, the cost of quality can be optimized by shifting left to ATE or right to SLT for improving fault coverage as required.”

SLT is particularly effective for advanced packaging because it simulates the device’s operational environment, testing multiple interconnected components together to expose issues that might only appear under combined workloads. System-level testing is essential for high-performance computing and AI, where packages include a combination of cores, memory, and potentially photonics.

“SLT complements ATE by enabling full-system evaluation at high speeds in mission-mode environments,” Hurtarte says. “It’s about moving from a purely functional test to one that ensures performance, quality, and reliability as a unit, especially when it comes to handling the growing requirements of HPC and AI-driven applications.”

The use of SLT is expected to expand further as packaging technology advances, with more manufacturers adopting this two-tiered strategy to balance speed, accuracy, and comprehensive performance testing.

Fig. 1: ATE and SLT serve as complementary solutions in test environments. Source: Teradyne

“SLT helps us bridge the gap between component-level functionality and system-level performance,” he says. “This two-tiered approach to testing — first with ATE, then with SLT — allows us to deliver more robust, reliable devices that meet both high data rates and high-density demands, while again optimizing the cost of quality.”

However, both ATE and SLT require ongoing innovation to meet the demands of advanced packaging. For ATE, the focus is on improving speed and parallel testing capacity to handle increasing volumes without sacrificing accuracy. Meanwhile, SLT emphasizes the need for thermal management and signal integrity under real-use conditions. The costs associated with failures post-packaging become a hindrance, making it essential to identify as many defects as possible prior to SLT — a task that becomes harder as packaging gets more complex.

Precision metrology for advanced packaging and hybrid bonding
As semiconductor packages become smaller and more complex, maintaining precision in metrology processes has grown increasingly challenging, as well. Inspecting solder bumps, which play a critical role in connecting semiconductor layers, exemplifies this difficulty. In recent years, solder bumps have shrunk from around 45mm to as small as 12mm, with silver content reduced to less than 1%. These reductions create challenges in measuring composition and consistency, which are key to preventing failures during reflow and bonding.

Shrinking dimensions are raising challenges everywhere. “Despite all the enthusiasm for interposers, organics still dominate the day-to-day business,” says Dick Otte, CEO of Promex Industries. “As we get down below these 50mm pitch numbers, down into the 10 to 20mm pitch kinds of stuff, that’s where the real issues are getting tough. Even the technologies that are going to dominate are up in the air, including how those are going to be done.”

Others agree. “Today’s advanced packaging demands push us toward smaller and more precise structures, so maintaining quality control in bump metrology becomes increasingly complex,” says Hoffman. “The need for precision in both measurement and process control is at an all-time high.”

To meet these demands, X-ray fluorescence (XRF) has become a core technique for determining the elemental composition of materials. By measuring the characteristic fluorescent (or secondary) X-rays emitted from a sample when excited by a primary X-ray source, XRF allows for precise, non-destructive analysis of thin films, layers, and elemental concentrations. This capability is essential for quality control and material characterization in advanced packaging.

“We are certainly seeing increased demand for more advanced technology nodes, particularly in the area of solder bumps,” explains Lior Levin, director of product marketing at Bruker. “As bump sizes shrink and silver content drops below 1%, the precision requirement has become critical.”

Consistency in these measurements is paramount. “Even minor deviations can lead to performance issues or reliability concerns in the final product, making metrology accuracy essential in advanced applications,” adds Hoffman.

Beyond solder bumps, hybrid bonding techniques address the need for <10mm pitch interconnects, enabling 3D die-to-die stacking configurations. Hybrid bonding’s ability to create finer interconnect pitches boosts performance and optimizes surface area usage, but success in these configurations depends heavily on surface preparations, such as managing oxide layers.

To handle the complexity of 3D packaging, manufacturers increasingly are turning to automated atomic force microscopy (AFM), which provides critical measurements of depth and roughness in multilayer structures. AFM delivers precision down to the sub-nanometer level, which is particularly valuable for assessing copper pad recess and dielectric topography to ensure bonding stability.

“In hybrid bonding, we’re addressing the complexities of ILD roughness and copper pad depth with AFM,” adds Hand. “AFM provides nanoscale accuracy over large areas, which is critical for successful bonding, particularly at the wafer’s edges.”

In addition to AFM, white-light interferometry has emerged as a crucial tool for high-resolution, non-contact measurements, especially for characterizing surface topography and step heights across different material layers. This technique is especially effective in hybrid bonding applications, where precise control over topography directly influences device performance.

“Atomic force microscopy provides an essential level of precision for measuring topography and depth,” says Peter De Wolf, director of technology and application development at Bruker. “This technology is helping engineers maintain bonding quality even as device architectures grow more intricate.”

High-density packaging continues to scale up, requiring metrology tools to handle larger scanning areas and more comprehensive profiling. This adaptability is critical for ensuring consistent quality in advanced configurations, where precision across both micro and macro features can make a significant difference in reliability.

“The capability to switch between nanoscale very localized measurements, and larger multi-millimeter fields of view is becoming increasingly valuable for hybrid bonding applications,” adds De Wolf. “This flexibility allows engineers to capture critical details at both the micro and macro levels, ensuring robust bonding quality across the entire wafer.”

Metrology advancements for 3D packaging
As engineers push into more complex 3D structures, maintaining measurement accuracy across layers becomes increasingly difficult. These structures require precision in monitoring parameters like via depth, alignment accuracy, and layer thickness, all of which are challenging when materials are densely stacked. As the density increases, so do the demands on metrology tools.

“AI has been driving the development of advanced packaging, and we see 2.5D and 3D ICs moving to more complicated die-to-wafer or wafer-to-wafer stacking structures,” says Peng. “This inevitably generates defects like voids in the interface of bonded wafers or cracking and chipping on the die from the pick-and-place process that traditional brightfield and darkfield illumination cannot detect. These new defects directly impact yield.”

“One of our main challenges in multi-layer fan-out structures is achieving repeatability within very tight tolerances — down to 0.1% for lateral and vertical CDs — as we increase density,” says Samuel Lesko, senior director for stylus and optical metrology at Bruker.

These tight tolerances are especially critical because variations in thickness or alignment can directly impact device performance. Testing and metrology solutions must capture accurate measurements, as well as adapt to the growing diversity in materials and complex structural requirements for different layers. For instance, the integration of photonics in 3D packages adds new dimensions of complexity.

“With 3D packaging, especially as we integrate more layers, mixed-signal components, and photonics devices, the ability to consistently achieve accurate measurements for each layer becomes crucial,” says Hurtarte. “Metrology tools in the front end of the semiconductor fabrication process need to be versatile enough to handle multiple materials, advanced nodes, and complex structures, ensuring precision across every layer.”

The need for a robust core strategy in managing the power and scalability of 3D packages is also a major challenge, particularly as AI-driven compute requirements continue to grow at an unprecedented pace.

“It’s all about test strategy for the optimization of cost of quality,” adds Hurtarte. “AI-driven compute requirements are doubling every four months, but Moore’s Law, which takes around 18 months to double transistor count, simply can’t keep up. This creates a widening gap between what wafer fabrication nodes can achieve and what heterogeneous integration can accomplish with multi-core packages.”

High aspect ratios in the vias, where features are narrow yet deep, also present a significant challenge in 3D packaging. These structures complicate depth measurements, necessitating improvements in metrology tools that can accommodate the unique geometries of these dense configurations. Collimated beam technology can provide depth measurements for high-aspect-ratio vias, even as they approach sub-micron diameters.

“By implementing a collimated beam approach, we’re able to achieve more reliable depth measurements for the increasingly deep vias used in advanced packaging,” says Christopher Claypool, senior director of R&D for FilmTek products at Bruker.

Other metrology tools, such as white-light interferometry, are playing an increasingly important role in 3D packaging, offering high-resolution, non-contact measurements. This technology provides detailed surface topography and step height measurements, which are crucial for hybrid bonding and other 3D integration processes.

The growing trend toward even smaller vias and thicker resist layers calls for enhanced tools to manage via depth and resist thickness with accuracy, especially in cases with high aspect ratios. Engineers also are focusing on improving yield by leveraging both test and metrology data more strategically. Testing strategies now incorporate parallel data gathering from multiple die in 3D packages, which allows for more efficient synchronization of outputs and defect detection.

Leveraging test and metrology data to improve yield
In the era of multi-die and fan-out wafer-level packaging, a comprehensive approach to defect detection and yield improvement is essential. Complex, layered devices require meticulous attention to each die’s performance to prevent cascading failures that can affect the entire assembly. Testing strategies that provide a holistic view of device performance are proving especially valuable, particularly in structures with repetitive die patterns where uniformity is critical to avoid variability that could impact end-use reliability.

“Data sharing is critical in multi-die assemblies, especially when we’re testing several identical die concurrently,” says Armstrong. “Implementing parallel structural testing allows us to capture vital V_min data and improve power supply performance, which directly improves yield.”

Advanced data processing and synchronization techniques play a pivotal role in detecting, localizing, and resolving issues efficiently. By gathering parallel data and synchronizing test outputs across identical die structures, testing teams can expedite yield analysis and zero in on potential failures. This approach is particularly useful for identifying defects early in the process, allowing teams to adjust and refine their methodologies for improved accuracy and efficiency. In doing so, they can catch failures that might otherwise impact several layers of interconnected devices.

“As packages get more complex, the need for integrated analysis tools and data collaboration becomes paramount,” says Hurtarte. “Combining and analyzing massive data outputs across multiple layers is essential. Engineers are seeing the value of quick, comprehensive insights that provide immediate feedback on both quality control and yield improvements.”

“We see high-bandwidth memory (HBM) devices as one of the best candidates to adopt high-density 3D interconnect technology,” says Nathan Peng, product marketing manager at Onto Innovation. “From HBM3 to HBM3e to HBM4, as demand for high-speed communication grows, it requires more I/O on the die and higher stacks (8 to 12 to 16) of the DRAM chips. In order to achieve this, the bump pitch needs to shrink from 25 µm to 20 µm to 16–18 µm, which will increase the number of bumps from 100 million to up to 150 million. As a result, the challenge becomes improved 3D inspection and metrology for process control of these small bumps.”

Automated post-processing of test data is becoming an invaluable tool for engineers, especially in cases where defect density and yield rates need to be optimized rapidly. The massive amounts of data generated by multi-die and multilayer packages demand processing methods capable of handling high-throughput analysis, which combines optical, X-ray, and other inspection methods. Automated processing ensures that engineers can quickly make decisions, correcting defects or optimizing process parameters in near real-time.

“We take measurements and offload data to the next software stage, using parallel processing to keep throughput high,” says Lesko. “Automated data review provides critical insights into quality control, enabling immediate feedback on defects.”

Leveraging data from both wafer and package testing stages allows for greater flexibility and a multifaceted approach to yield improvement. Automated defect analysis tools, combined with artificial intelligence and machine learning, increasingly are aiding in defect prediction and trend analysis, enhancing manufacturers’ ability to implement preventive strategies. This approach enables teams to refine their processes in response to actual in-process feedback rather than relying solely on preset parameters, making testing strategies more dynamic and adaptable.

“Using integrated data from various sources in advanced packaging can really differentiate a fab,” says Sean King, product manager for enterprise software at Onto Innovation. “A centralized data platform seamlessly integrates data from not only inspection and metrology tools, but other relevant data from the manufacturing process to immediately deliver process data and impactful insights to users. Once data is in the platform, users have advanced analysis, pattern recognition, and report-generating features at their fingertips.”

“The need for precision timing and error correction has added another layer of complexity,” says Siemens’ Neerkundar. “Incorporating AI and machine learning helps to analyze data from different points, especially in real-time scenarios, to predict potential issues and proactively mitigate them.”

For multi-layered and high-density packages, the role of yield optimization becomes even more challenging as device structures scale up in complexity. Combining various metrology methods allows for deeper analysis of factors like interconnect integrity and material consistency across entire wafer or package assemblies. White-light interferometry, X-ray fluorescence, and atomic force microscopy (AFM) provide engineers with nuanced data on surface variations and defect density, which is essential for tracking yield fluctuations across production cycles.

“The capability to perform both micro and macro-level metrology on the same die is key,” adds De Wolf. “Hybrid bonding applications, for example, demand both nanoscale precision and larger field analysis, allowing us to identify and correct yield-impacting issues early on.”

Collaborative ecosystems
Looking forward, collaborative ecosystems will play an increasingly essential role in advancing the capabilities of advanced packaging, particularly as the industry begins to form application-specific silos. This segmentation is driven by the diverse needs of advanced packaging technologies and the high costs of specialized equipment and expertise. With multiple packaging techniques now emerging — each tailored to specific applications like high-performance computing, AI, and automotive — the industry is moving toward segmented ecosystems where vendors specialize to address distinct requirements.

“Different manufacturers are beginning to migrate toward what works best for their specific applications,” says Hoffman. “It’s not just about having the right tools. It’s about building expertise in a particular type of packaging to maximize performance and efficiency.”

This trend toward specialization reflects the reality that the cost and complexity of equipment for advanced packaging can be prohibitive. As a result, companies are beginning to focus on certain packaging approaches, such as fan-out wafer-level and chiplet-based designs, while developing targeted capabilities that allow them to cater specifically to application-driven needs. This shift allows businesses to deepen their expertise, foster innovation within specific niches, and potentially achieve greater economies of scale by standardizing on one or two packaging methodologies.

The complexity of integrating diverse components, especially in chiplet designs, is pushing the industry toward modular approaches where interoperable components from various vendors can integrate seamlessly. However, the need for open ecosystems that enable cross-functional collaboration also brings significant hurdles, particularly around data sharing and intellectual property (IP). While collaboration is essential for innovation, IP protection remains a barrier to fully open partnerships.

With each application area requiring specific capabilities, companies are finding it increasingly advantageous to form partnerships and alliances, pooling resources to address the wide-ranging demands of advanced packaging. Collaborative ecosystems that include specialized equipment vendors, software providers, and foundries could streamline development processes, reduce costs, and accelerate time to market.

“Collaborative ecosystems are no longer optional,” says Hurtarte. “They’re becoming critical to staying competitive. By sharing expertise and resources, companies can keep pace with rapid advancements without bearing the full cost of development independently.”

Advancements in metrology and test strategies are shaping the landscape, as companies push for increasingly precise measurement and data integration to enhance both yield and performance in these complex, application-specific packages. Technologies like quantum metrology are on the horizon, promising transformative possibilities in measurement accuracy and defect detection. These innovations, alongside enhanced data-sharing protocols within collaborative ecosystems, could redefine the limits of semiconductor packaging.

“The complexity of keeping Moore’s Law going is exponentially increasing,” says Hoffman. “We’re just beginning to see the impact of these advanced technologies on metrology and test solutions.”

Conclusion
As the semiconductor industry continues to push the boundaries of device performance and integration, advanced packaging has become a critical area of focus. The challenges of ensuring signal integrity and thermal performance in increasingly dense and high-frequency devices have driven innovation in both testing methodologies and thermal management solutions. The shift from traditional ATE to system-level testing reflects the need to evaluate devices in conditions that closely mimic real-world applications, particularly for complex 3D and heterogeneous packages.

Precision in metrology has never been more crucial, with technologies like XRF, AFM, and white-light interferometry enabling engineers to measure and control features at the nanoscale. These advancements are essential for the success of hybrid bonding and other advanced packaging techniques that demand exceptional accuracy across multiple layers and materials. Leveraging data from both testing and metrology allows for improved yield and reliability, as engineers can identify and address defects more efficiently.

The industry’s move toward collaborative ecosystems and specialization acknowledges the increasing complexity and cost of advanced packaging. By pooling resources and expertise, companies can tackle the challenges of integrating diverse components into advanced packages.

Related Reading
Signals In The Noise: Tackling High-Frequency IC Test
Millimeter-wave frequencies require new test approaches and equipment; balancing precision with cost-efficiency is the challenge.
Metrology And Inspection For The Chiplet Era
Recent developments address imminent needs of advanced nodes and packages, but not all the pieces are in place yet.
X-ray Inspection Becoming Essential In Advanced Packaging
Improvements in speed and precision have transformed a research tool for studying defects in chips into an industry workhorse.
Speeding Up Metrology At Advanced Nodes
Demand for higher reliability requires more advanced and historically slow equipment and methodologies, but improvements are on the way.