Assembly Design Rules Slowly Emerge

Process design kits (PDKs) play an essential in ensuring that silicon technology can proceed from one generation to the next in a manner that design tools can keep up with. No such infrastructure has been needed for packaging in the past, but that’s beginning to change with advanced packages.

Heterogeneous assemblies are still ramping up, but their benefits are attracting new designs. “Chiplets and heterogeneous integration allow disaggregation of monolithic SoCs by partitioning to mix and match different silicon and reusing IP to build systems having more flexibility, optimize the performance, and reduce cost,” said Lihong Cao, senior director at ASE Group in a presentation at the OCP Summit.

With 2.5D and 3D designs, the package is every bit as much of the overall solution as the components inside, so design verification no longer stops at the edge of a die. Manufacturing is also far more complex, and foundry and assembly houses need better ways of articulating the best ways to ensure that a new product will be manufacturable with good yield.

Variously called assembly design kits (ADKs) or package-assembly design kits (PADKs), such files document the capabilities and rules for building an advanced package. One influential player is putting its weight behind it: “All the new [U.S.] government programs call for it,” said John Park, product management group director for advanced IC packaging at Cadence. The question is whether everyone will agree on what should be in there, and what it should look like.

What’s available now is part-way to an ADK, but it lacks the rigor and stability of a PDK. “People are used to this nice, formal PDK,” said Park. “When you go to packaging, it’s all over the map, and it changes all the time.”

More than just leadframes and substrates
The simplest packages historically have enclosed two items — a die and a leadframe, interconnected by bonding wires. More recent (but still historical) larger packages such as ball grid arrays (BGAs) have relied on a substrate that typically holds a flip-chip die. That substrate is essentially a small printed circuit board (PCB). Bumps on the die mate with pads on a substrate. The signals run on substrate interconnects from the die to the package balls.

Substrate designers check out their pad and interconnect placement by submitting the substrate’s Gerber plots to an outsourced assembly and test (OSAT) house, which checks them to ensure that the proposed substrate will yield well when built. “All you need is a CSV file and a set of design rules and you can get started on a substrate,” said Shawn Nikoukary, senior director in Synopsys’ System Solutions Group.

Advanced packages still have substrates, and they go through the same traditional process. But those packages contain many other components, potentially including multiple chiplets, passive devices, microelectromechanical systems (MEMS) or optical components, and an interposer. The interposer often is the only component connecting directly to the substrate. The other connections go through the interposer. And the overall performance of the co-packaged subsystem depends on everything from die details to component placement within the package.

Yet another sign-off
Because of the complexity of the potential interactions between components, advanced packages now require a full sign-off process, and it’s for more than manufacturability. Designs still must be checked for sufficient yield, but a simple Gerber evaluation is no longer enough for any verification beyond the substrate. “These newer tools require text files and lots of setups and methodology, and it’s a lot more complicated,” said Synopsys’ Nikoukary.

The floor plan establishing the layout of components in the package must be checked to ensure it is buildable, with appropriate clearances for tools. A floor plan may require two or three iterations to settle out. This can affect the chip design, as well, so this effort cannot be pushed to the last minute.

“You need to have assembly rules that say how high you can stack your chiplets,” said Cadence’s Park. “How close to one another can you put your chiplets? How close to the edge of the substrate can you put your chiplets?”

In some cases, a standard module height exists. “HBM is placed alongside the AI accelerator, and therefore there is a standard height limitation of 775 microns for the thickness of the memory stack and also the GPU die,” said CheePing Lee, senior technical director for advanced packaging at Lam Research.

Floor-planning decisions often are made early in the design flow. “Chiplet designs are locked at tape-out, but the push for co-optimization means that certain aspects are decided earlier,” said Anthony Mastroianni, advanced IC packaging solutions architect at Siemens EDA. “Front-end constraints, like pin placements and power delivery requirements, need to align with package capabilities well before tape-out. The goal is to reduce surprises later by addressing these interdependencies early in the design flow.”

Redistribution layers (RDLs) often are added to a die when necessary to spread bumps around for the necessary bump pitches. The stack-up — and even the materials employed — must be verified to ensure that assembly can proceed smoothly. Vias, whether they are through-silicon (TSVs) or through-interposer (TIVs), must be checked out. Even the functional partitioning between multiple chiplets must be blessed.

“We work with our customers to find out what their stack-up is going to be, how many layers they’re thinking,” said Ruben Fuentes, vice president of worldwide design at Amkor. “Then we create a custom ADK for them on the fly. We provide them with a starting design database and layer conversion files so that they understand how the layer mapping works. As long as they run our ADK while designing the package, it guarantees that we’re going to be able to manufacture it for them.”

Various aspects of an advanced package may interact in unexpected ways. “The bump height dictates some spacing rules, depending on type of bump and spacing that you use,” said Nikoukary. “It also dictates how close these components can get.”

More than manufacturability
Manufacturability is but one of many elements that must be verified prior to sign-off. “There are manufacturing rules, and then there are design rules,” said Nikoukary.

Probably the most important mechanical factor to be checked out is the ability of the package to dissipate enough heat to keep the contents operating within spec. This is of particular concern with high-powered processors and HBM stacks, where positioning of chips really matters. For example, heat degrades HBM performance, so keeping some distance between a hot processor and its memory is helpful, but that must be weighed against any performance loss due to longer traces. If stacking more than one die, it’s best if the hottest one goes on the top of the stack so that its heat can be more easily removed.

Mechanical stress has become an important factor due to the many microbumps and bumps that must have sufficient co-planarity to make reliable connections to a flat surface such as an interposer or substrate. “You need to measure the height of all these various micro-bumps,” said Lam’s Lee. “Are they flat or are they not flat? They are specified to be as flat as possible, because if you have one or a couple of micro-bumps that are too tall, they will join with the pads and cause the rest of the lower bumps to not join to the other pads.”

Thermal stress during assembly can lead to warpage due to multiple materials with different coefficients of thermal expansion (CTEs), but this depends on the assembly process. Standard bump reflow subjects an entire assembly to the reflow heat, and all the components will expand. Thermocompression bonding subjects only the die being bonded to that temperature, sparing the other components. But it proceeds die-by-die, making it a slower and thus more expensive process than simply using a reflow oven that can reflow an entire tray of packages at once.

Electrical verification
Some electrical traces also must be verified — SerDes, in particular — due to the high frequencies at which they operate. Electrical noise passing through any of the materials, whether originating inside or outside the package, can degrade signal quality, closing the eye on an eye diagram. Some signals may need to be separated by ground traces to combat crosstalk.

“We do RLC evaluation and electrical route checks, as well stress simulation,” said Cao. “In SerDes designs, we [analyze] the insertion return loss and the power domain network design.”

Electromigration can result in long-term failures, so the entire assembly must be checked to ensure that current densities remain in a safe range.

All this verification theoretically must be performed on the entire assembly, from the first transistor to the last bump. PCB design tools cannot deal with the number of database entries that an advanced package has, which today are in the millions. IC design tools, however, have been built to work on the enormous databases necessary for the largest chip designs, so they handle everything but the substrate.

But even IC design tools can’t process a flat representation of the entire assembly, so chunks of the design are abstracted to make verification tractable in a reasonable time. In particular, logic-versus-schematic (LVS) and design-rule checking (DRC) are performed on the package components.

The number of suppliers also matters when planning an advanced package. “We’re paying more attention to supply chain constraints and ensuring designs are feasible within the available material and manufacturing technologies,” added Mastroianni.

Herding package rules
The package equivalent of the PDK, which we’ll call an ADK, is at present a loose concept being managed on an ad hoc basis. Developers, foundries, and OSATs are establishing rules for reliable production, but they’re determined on a project-by-project basis and lack a consistent structure. The types of rules they include go beyond what a silicon PDK contains because there’s much more going on than just semiconductor processing. That said, the sheer number of rules is smaller than what might be necessary for an advanced-node PDK.

“We’re including not only the standard stuff, like line and space, but we’re also doing assembly checks in there,” said Fuentes. “We could check to see if our capacitor sizes are correct. But I would say that [PDKs] are much larger.”

There is no agreed upon format for ADKs, even though the data they contain overlaps with that of a PDK. “Each OSAT or foundry is going to have to develop its own,” said Fuentes. “But it’s using the same functions that are used on the on the IC side.”

The format may be heavily influenced by EDA tools that ingest the files, as is the case with PDKs. “For Calibre (Siemens’ DRC tool), we use their SVRF format,” continued Fuentes. “It’s a specific format that they created that they have all their customers designed into. It ensures that their tool can read the ADK.”

The lack of a single source for the ADK also can be challenging. Some rules come from foundries building silicon interposers. Organic interposers tend to come from OSATs, although not all OSATs possess the tooling necessary for the most advanced line/space rules. All involved foundries, OSATs, and any other suppliers of other components such as HBM have something to contribute to the overall assembly plan. So while there is no agreed-upon format, there’s also not one source for all the data.

“More and more OSATs — and even substrate houses — are getting into advanced packaging, offering organic advanced packages into which you embed silicon bridges,” said Synopsys’ Nikoukary. “But those design rules are little bit different coming from OSATs and substrate houses, and the format is different.”

Elusive standards
PDKs never have been formally standardized. There are open PDK projects, but given the limited number of foundries and EDA tool vendors, practical PDK formats are negotiated between each foundry and tool vendor. At present, standardizing doesn’t appear to be a high priority, even given the enormous chip volumes shipping today.

“There’s never perfect standardization,” said Keith Lanier, director of technical product management at Synopsys. “There were attempts at getting there, but they never made it 100%, and the same thing may happen with assembly design kits.”

For all their headlines, advanced packages represent few of the chips being shipped today. That keeps the burden reasonable. But if such techniques go mainstream, marshaling the necessary information from the many sources to a variety of assembly houses is likely to become unmanageable. A process that negotiates a set of rules individually per project with all parties involved can be extremely inefficient.

There are loose discussions of trying to standardize ADKs. “Can you bridge the gap between the PDK and ADK and make them more similar, or even overlap more completely?” asked Lanier.

Regardless, the focus is now on how to push the technology forward. Capabilities are changing quickly enough that it probably feels premature for standards. As the technology settles out, if it remains tightly controlled by a few companies, then a standard may be viewed negatively for making it too easy to move between vendors.

The fact that the tools that will process the ADKs are well-established also creates a barrier to change. “Part of the challenge is getting some of the older tools that are out there to be able to support a standard,” noted Lanier.

But the prospect of an open chiplet market may add impetus. “To enable a true open ecosystem for heterogeneous designs, the design and manufacturing teams will need to collaborate on a set of common design rules and materials which meet both the design needs and the manufacturability of the respective package components,” said Mastroianni. “This open ecosystem will require new open formats, design kits, and design methods to define and deploy this new user driven supply chain.”

ADKs are coming
The number of interactions and dependencies for building a manufacturable advanced package is making it necessary to specify the many rules. OSATs will not want to take on projects that will have poor yield. IC tool vendors need a way to ingest the rules to be verified. And no one in the project wants to discover fatal flaws late in the process. On top of that, the U.S. government requires ADKs for new projects.

Part of the challenge now is education. “There’s a lot of educating, telling customers what an ADK is, why it’s so important, and then trying to get them all set up,” said Fuentes. “Typically, package designers don’t have any knowledge of ADKs. It’s all really new to the OSAT world.”

And the rapid pace of development suggests ADKs will continue evolving. “There are still a lot of unknowns in the packaging world,” Fuentes noted. So ADKs should continue to progress rapidly as the technology itself does. We may or may not see standardized ADKs, but we will see ADKs in one form and/or another.

—Laura Peters contributed to this report.

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