Atomic Layer Etch Finally Emerges

The migration towards finFETs and other devices at the 20nm node and beyond will require a new array of chip-manufacturing technologies. Multiple patterning, hybrid metrology and newfangled interconnect schemes are just a few of the technologies required for future scaling.

In addition, the industry also will require new techniques that can process structures at the atomic level. For example, a transistor gate width could consist of only 20 atoms at the 7nm node, compared to 140 atoms at 20nm. So, to help manipulate the atoms in future devices, chipmakers will likely require a new and disruptive technology called atomic layer etch.

Atomic layer etch, sometimes known as ALE, is a next-generation plasma etch technology that enables layer-by-layer, or atom-by-atom, etching for IC designs. ALE is also related to atomic layer deposition (ALD). ALD has been in IC production for years, but ALE has been a solution looking for a problem and stuck in R&D labs for nearly two decades.

Now, after years of hype, ALE appears to be moving from the lab to the fab. And in fact, the plasma etch tool titans, such as Applied Materials, Lam Research, TEL and others, are readying ALE-enabled tool technologies for customers.

“People have been asking about atomic layer etching for years, but it’s been a difficult thing to do,” said Bradley Howard, vice president of the Etch Advanced Technology unit at Applied Materials. “Finally, the industry has the ability to make it happen. In logic, for example, when you start to get to 10nm, you will start to see processes that include ALE or ALE-like technologies. At 7nm, it’s a big inflection point toward getting these types of capabilities inserted.”

ALE will not replace the traditional plasma etcher in the fab, but the newer technology will be required for the most advanced structures, added Thorsten Lill, vice president of emerging technologies and the Systems Group at Lam Research. “We are in an era of atomic scale dimensions,” Lill said. “We are saying that atomic level fidelity and sub-10nm structures will require new approaches in plasma etch. So we believe ALE is necessary. Certain applications can only use ALE. Without it, we can’t move forward.”

More specifically, ALE is a way to selectively and precisely remove targeted materials. “This could be used for things like dummy gate removal for fin replacement as the industry moves to new gate materials like InGaAs, or for simply creating more perfectly shaped fins to support continued scaling,” said Weston Twigg, an analyst with Pacific Crest Securities. “It could also be very useful in creating nanowires for potential 5nm insertion by removing all of the material around and under the wire. This is very interesting stuff, but it’s early, and we expect a tradeoff somewhere, likely in throughput.”

Etching the surface
Etch, the process step that removes materials from the wafer to create the features of a device, is a critical but somewhat unheralded tool in the fab. The overall plasma etch market represents 12% to 14% of the total wafer fab equipment (WFE) business, according to Lam Research. In total, the WFE market is expected to reach $30.8 billion in 2014, up 13% from $27.3 billion in 2013, according to Gartner.

Going forward, etch is becoming more important in the flow. For example, extreme ultraviolet (EUV) lithography remains delayed, forcing chipmakers to deploy multiple patterning techniques starting at 20nm. Multiple patterning, in turn, adds 30% more etch steps in the logic flow, according to Pacific Crest Securities.

For decades, meanwhile, chipmakers have used the same basic plasma etcher, sometimes called reactive ion etch (RIE), in the fab. In general, the etcher is used for two main and separate applications—conductor and dielectric. Conductor etch helps shape the active materials, while dielectric etch carves patterns in insulating materials to create barriers.

In RIE, a tool combines many gases in the reactor at the same time. Basically, ALE also provides conductor and dielectric etch, but the newfangled technology handles these functions at a finer scale or at the atomic level. And unlike RIE, ALE performs single unit steps to achieve set outcomes, which may impact the overall throughput of the process.

Today’s plasma etchers remain the workhorse tools in the fab, but there are some new challenges as chipmakers migrate to finFETs and other devices. In finFET production, for example, one challenge is to make fin structures with consistent heights during the etch process. A faulty etch step could lead to variability with the fin structures.

“That was one of the things that drove people to look at the need for atomic layer etching,” Applied’s Howard said. “The topography (in fin structures) drives an over etch. And if you over etch to clear over more topographies, you are exposing your device to potentially more damage.”

ALE, in theory, minimizes the damage in the etch flow. “If you are talking about a 45nm transistor and you have a nanometer of damage on each side, that’s probably not a huge problem. But if you have a 10nm or 7nm device, and you’ve got one nanometer of damage on each side, that’s a large bulk of what that device is in terms of damaged material. Anything you can do to reduce the damage characteristics, and don’t have to use aggressive cleans afterwards, is an important part going forward,” Howard said.

Another driver for ALE is also apparent. The industry is moving towards atomic-level scaling. “The features are getting smaller,” Lam’s Lill said. “At 7nm, we will basically have about 20 atoms to create a transistor of this width. If you account for the variability for a device at 7nm at 1%, and (you account for) a CD budget, that is now basically seven angstroms. Now, we are talking about two atoms or two atomic bonds. 5nm would be four atoms. It’s very obvious, but at the end, there will be only one atom left.”

A mug of ALE
So for atomic-level scaling, the next-generation etch solution is clear—ALE. The big question is what can ALE do in the fab and will it achieve the same success as ALD. For years, ALD has been used to scale the capacitor in DRAMs as well as developed the high-k/metal-gate stack for logic devices.

“In atomic layer deposition, you come in and saturate a surface with one reactant. Then, you come in with another reactant. That becomes a single layer of material. You cycle through this multiple times to create many layers of atomic layers,” said Applied’s Howard. “Atomic layer etching is taking that in reverse. You want to have the etch occur only at the very surface, effectively one layer at a time or one atomic layer at a time. What you are doing is getting a reaction or change on the surface. Then, you remove that reactant material. You go through that same cycle multiple times. So in the end, atomic layer etching gives you the opportunity to have very low damage and polymer free surfaces at the end of etching.”

Unlike ALD, ALE has not moved into mass production. Among the challenges for ALE has been to control the pulsed power at low energies. “We know how to do that now,” he said. “There has been a lot of improvement on etch processing control, ion energies and pulsing of gases.”

Going forward, Applied envisions that ALE will likely appear in a cluster tool. That tool could have one or several dedicated ALE chambers. The same tool could also have dedicated and separate RIE and clean chambers, in which ALE, RIE and the cleans are running in conjunction as a mean to perform separate tasks.

“ALE won’t take over everything in etch,” Howard said. “RIE will be around for the foreseeable future for certain applications. If you have to etch a substantial amount of material, you probably do not want to use ALE. That takes time,” he said.

“On the other hand, you will see ALE come in for both conductor and dielectric etching. For conductor, ALE will play in the regular gate and fin formation, or any engineering on the shaping of the fins,” he said. “For the dielectric side, when you make a contact, you typically come down to a stopping layer. And then you punch through the stopping layer. If you could have a very low damage process that etches through that stop layer, and gets you down to your contact surface, you can improve the contact resistance and the device matching capabilities.”

Lam’s Lill agrees that ALE will not replace RIE. “We will offer both technologies in one reactor,” Lill said. “We think they will be complementary for certain applications. But we are already seeing the transition (to ALE) in certain applications.”

ALE could be used for 3D NAND, sub-20nm DRAMs and finFETs, but there are still some challenges before ALE is running in the production fab. “There are still three grand challenges left,” Lill said. “One is that there are no secondary unintended reactions for ALE. For example, we don’t want extreme UV radiation in the reactor. Second, we want the unit steps to be discrete. And finally, we need self-limiting single unit steps. They are very difficult to find.”

There are other issues as well. “One of the key challenges in getting ALE into the fab is the smart chemistry aspect of this technology,” said Craig Huffman, atomic layer etch and clean engineer at Sematech. “The semiconductor world has used HF or hydrofluoric acid (in traditional etch). HF has a very good reaction with Si0², but it has almost zero reaction to silicon. If you expand that into the new materials that will be used in transistor fabrication moving forward, you can imagine chemistries along the same lines.”

In the distant future, meanwhile, ALE could help pave the way to future devices, such as III V finFETs, gate-all-around FETs and others. III V finFETs are slated for 7nm, while gate-all-around could appear at 5nm. “III V might be one of the materials that ALE will play a key role in,” said Dae-Hyun Kim, ALE project manager at Sematech. “In case of the nanowire, the physical dimensions are below 10nm or so. It will be extremely important to control any geometry of that circumstance. Losing 1nm out of 10nm means 10% change or variation.”

ALE, according to Kim, could be used in the development of futuristic two-dimensional materials, such as graphene, boron nitride, and the transition metal dichalcogenides (TMDs). Two TMD materials, molybdenum diselenide and molybdenum disulfide, are both attractive materials for use in future FETs.

“There are applications for what we would describe as vanilla materials like oxide nitrides all the way to exotic materials,” added Richard Hill, technology manager at Sematech. “So, ALE was once a solution looking for a problem. That problem has come of age. So we see a long and healthy future for ALE.”