Week in Review – IoT, Security, Autos
By Jeff Dorsch - 27 Sep, 2019 - Comments: 0

Products/Services Achronix Semiconductor joined Taiwan Semiconductor Manufacturing’s IP Alliance Program, part of the foundry’s Open Innovation Platform. Achronix’s Speedcore eFPGA IP is available today on TSMC 16nm FinFET Plus (16FF+) and N7 process technologies, and it will be soon available on TSMC 12nm FinFET Compact Technology (12FFC). Cadence Design Systems announced that its di... » read more

Week In Review: Design, Low Power
By Jesse Allen - 27 Sep, 2019 - Comments: 0

eSilicon debuted its 7nm high-bandwidth interconnect (HBI)+ PHY IP, a special-purpose hard IP block that offers a high-bandwidth, low-power and low-latency wide-parallel, clock-forwarded PHY interface for 2.5D applications such as chiplets. HBI+ PHY delivers a data rate of up to 4.0Gbps per pin. Flexible configurations include up to 80 receive and 80 transmit connections per channel and up to 2... » read more

The Great Data Flood Ahead
By Ed Sperling - 26 Sep, 2019 - Comments: 1

The number of devices connected to the Internet is expected to exceed 1 trillion devices over the next decade or so. The timeline is a bit fuzzy, in part because no one is actually counting all of these devices, but the implications are pretty clear. A data deluge of biblical proportions is headed our way, and so far no one has any idea of what to do with all of it. From a system-level s... » read more

Survival Of The Cheapest?
By Brian Bailey - 26 Sep, 2019 - Comments: 0

We all want the best solution to win, but that rarely happens. History is littered with products that were superior to the alternatives and yet lost out to a lessor rival. I am sure several examples are going through your mind without me having to list them. It is normally the first to volume that wins, often accelerated by copious amounts of marketing dollar to help push it against headwinds. ... » read more

High-Level Design And High-Level Verification
By Dominik Strasser - 26 Sep, 2019 - Comments: 0

Not so long ago, some EDA vendors were painting a very attractive picture of chip design in the then-near future. The idea was that an architectural team would write a single description of the complete system in some high-level language, usually C/C++/SystemC, and that a new class of EDA tool would automatically partition the design into hardware and software, choosing the functionality of eac... » read more

Toward A Lingua Franca For Intelligent System Design
By Frank Schirrmeister - 26 Sep, 2019 - Comments: 1

As the EDA industry is moving up further and further towards the intelligent design of full systems, this year’s Forum on Design Languages (FDL) offered a great update on the status quo with regard to where languages fit into this transition. It looks like the next step will not be one universal language as previously targeted back when there was a flurry of introductions of new programming m... » read more

Fast-Track Your Early SoC Design Exploration And Verification
By Nermeen Hossam - 26 Sep, 2019 - Comments: 0

By Nermeen Hossam and John Ferguson Most advanced node system-on-chip (SoC) designs are very large, and very complex. They typically contain many blocks and intellectual property (IP) that perform specialized functions, such as computation, internal communications, and signal processing. These blocks are often built by separate teams or IP suppliers, and integrated into the SoC layout. Howev... » read more

Open ISAs Gaining Traction
By Ann Mutschler - 26 Sep, 2019 - Comments: 0

Open instruction set architectures are starting to gain a foothold, often in combination with other processors, as chipmakers begin to add more specialized compute elements and more flexibility into their designs. There are a number of these open ISAs available today, including Power, MIPS, and RISC-V, and there are a number of permutations and tools available for sale based on those archite... » read more

No More Pizza! The Power Of HPC To Answer: “What’s For Dinner?”
By Ruben Molina - 26 Sep, 2019 - Comments: 0

The other night my wife and I were trying to pick a place we could both agree on for dinner. If you’ve ever been in this situation, you know it can be a difficult problem to solve. I decided to short circuit the usual torture by asking our virtual assistant for a solution. “Hey [Virtual Assistant], where’s a good place to eat?” Thus ensued 15 minutes of intermittent, wrong answers, misc... » read more

The Growing Impact Of Portable Stimulus
By Brian Bailey - 26 Sep, 2019 - Comments: 0

It has been a year since Accellera's Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has had, and the future direction of it, with Dave Kelf, chief marketing officer for Breker Verification Systems; Larry Melling, product management director for Cadence; Tom Fitzpatrick, strategic verification architect for Mentor, a Siemen... » read more

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