No More Pizza! The Power Of HPC To Answer: “What’s For Dinner?”
By Ruben Molina - 26 Sep, 2019 - Comments: 0

The other night my wife and I were trying to pick a place we could both agree on for dinner. If you’ve ever been in this situation, you know it can be a difficult problem to solve. I decided to short circuit the usual torture by asking our virtual assistant for a solution. “Hey [Virtual Assistant], where’s a good place to eat?” Thus ensued 15 minutes of intermittent, wrong answers, misc... » read more

The Growing Impact Of Portable Stimulus
By Brian Bailey - 26 Sep, 2019 - Comments: 0

It has been a year since Accellera's Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has had, and the future direction of it, with Dave Kelf, chief marketing officer for Breker Verification Systems; Larry Melling, product management director for Cadence; Tom Fitzpatrick, strategic verification architect for Mentor, a Siemen... » read more

Long And Longer Reach SerDes – On The Road Again
By Mike Gianfagna - 26 Sep, 2019 - Comments: 0

We’ve had the pleasure of participating in two events over the past two weeks. I wouldn’t recommend doing two major shows back-to-back, but it has been exhilarating and quite interesting. Our “road trip” began last week in Mountain View for the second annual AI Hardware Summit. You’ve probably noticed you can go to an AI-related show every week (or more) if you like. The trick is to f... » read more

A Specification-Driven Methodology For The Design And Verification Of Reset Domain Crossing Logic
By Mentor, a Siemens Business - 25 Sep, 2019 - Comments: 0

Reset architectures have increased in complexity along with SoC designs. Sadly, traditional reset design and verification techniques have not evolved to address this increase in complexity. In order to avoid ad-hoc reset methods, this paper presents a three-step specification-driven methodology that provides a requirements-based approach for reset domain crossing design and verification. To ... » read more

Better Benchmarks Through Compiler Optimizations: Codasip Jump Threading
By Codasip - 25 Sep, 2019 - Comments: 0

The architectural efficiency of embedded processor IP is measured by a small set of industry standard benchmarks, that even though often bear little correlation to real workloads, continue to persist. The most popular benchmarks are Dhrystone and CoreMark. An interesting observation regarding these test suites is that the performance numbers continue to improve for a given architecture, even... » read more

Opposites Attract: IP Standardization vs. Customization
By eSilicon - 25 Sep, 2019 - Comments: 0

Have you had a look lately at an autonomous driving SoC? Have you noticed, besides the cool machine learning stuff, the grocery list of third-party IP that goes into it? It is a long, long list, composed of pieces both big and small and quite diverse. For example, interface and peripheral PHYs and controllers, memories, on-chip interconnects, PVT monitors and PLLs. In some highly-publicized exa... » read more

Celsius Thermal Solver
By Cadence - 25 Sep, 2019 - Comments: 0

The Celsius Thermal Solver environment enables all aspects of thermal analysis to quickly and accurately identify thermal problems in IC packages, PCBs, and electronics systems. It features an innovative massive parallel solver technology that enables simulation speeds up to 10 times faster than conventional thermal simulators, with significantly reduced memory usage. It includes a powerful fin... » read more

Best Practices for Traceability of Functional Safety Requirements In Automotive IP & SoCs
By Synopsys - 25 Sep, 2019 - Comments: 0

Automotive functional safety systems continue to incorporate complex features to meet wide range of consumer demands. Developing functional safety systems, including all the components such as the system-on-chip (SoC) and IP, hinges on the ability to meet the stringent automotive functional safety requirements such as definition, implementation, verification, and validation. Functional safety S... » read more

How FinFET Device Performance Is Affected By Epitaxial Process Variations
By Jacky Huang - 25 Sep, 2019 - Comments: 0

By Shih-Hao (Jacky) Huang and Yu De Chen As the need to scale transistors to ever-smaller sizes continues to press on technology designers, the impact of parasitic resistance and capacitance can approach or even outpace other aspects of transistor performance, such as fringing capacitance or source drain resistance. The total resistance in a device is comprised of two components: internal re... » read more

Why Data Is So Difficult To Protect In AI Chips
By Ed Sperling - 25 Sep, 2019 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss a wide range of hardware security issues and possible solutions with Norman Chang, chief technologist for the Semiconductor Business Unit at ANSYS; Helena Handschuh, fellow at Rambus, and Mike Borza, principal security technologist at Synopsys. What follows are excerpts of that conversation. The first part of this discussion ca... » read more

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