New Embedded FPGA Compiler Maximizes IP Implementation Efficiency
By Jayson Bethurem - 11 Jul, 2024 - Comments: 0

When designing IP for system-on-chip (SoC) and application-specific integrated circuit (ASIC) implementations, IP designers strive for perfection. Optimal engineering often yields the smallest die area, thereby reducing both cost and power consumption while maximizing performance. Similarly, when incorporating embedded FPGA (eFPGA) IP into a SoC, designers prioritize these critical factors. ... » read more

On-Chip Communication For Programmable Accelerators In Heterogeneous SoCs (Columbia, IBM)
By Technical Paper Link - 10 Jul, 2024 - Comments: 0

A technical paper titled “Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures” was published by researchers at Columbia University and IBM Thomas J. Watson Research Center. Abstract: "We present several enhancements to the open-source ESP platform to support flexible and efficient on-chip communication for programmable accelerators in het... » read more

Analysis Of The On-DRAM-Die Read Disturbance Mitigation Method: Per Row Activation Counting
By Technical Paper Link - 10 Jul, 2024 - Comments: 0

A technical paper titled “Understanding the Security Benefits and Overheads of Emerging Industry Solutions to DRAM Read Disturbance” was published by researchers at ETH Zürich and TOBB University of Economics and Technology. Abstract: "We present the first rigorous security, performance, energy, and cost analyses of the state-of-the-art on-DRAM-die read disturbance mitigation method, Per... » read more

Startup Funding: Q2 2024
By Jesse Allen - 10 Jul, 2024 - Comments: 0

AI drew more investors to the chip industry in Q2. Four AI-focused chip startups receiving rounds of more than $100 million, targeting data center ASICs for transformers, highly flexible platforms for the embedded edge, dataflow processors, and mixed-signal neuromorphic chips. In-memory computing also helped boost AI, with three companies either incorporating it into their chips or providing sp... » read more

Blog Review: July 10
By Jesse Allen - 10 Jul, 2024 - Comments: 0

Cadence's Paul Graykowski suggests using real number modeling to streamline digital mixed-signal verification using logic simulators and hardware emulators. Siemens' John McMillan and Microsoft's Amit Kumar introduce the basics of 3D-IC, describe the flow and data management challenges, look at the evolution of TSMC 3DBlox 1.0 and 2.0, and detail a physical verification and reliability analy... » read more

Roadmap To Neuromorphic Computing (Collaboration of 27 Universities/Companies)
By Technical Paper Link - 09 Jul, 2024 - Comments: 0

A technical paper titled “Roadmap to Neuromorphic Computing with Emerging Technologies” was published by researchers at University College London, Politecnico di Milano, Purdue University, ETH Zurich and numerous other institutions. Summary: "The roadmap is organized into several thematic sections, outlining current computing challenges, discussing the neuromorphic computing approach, ana... » read more

The Semiconductor Revolution And The Role Of Adaptable Testing
By Juan Valdivia - 09 Jul, 2024 - Comments: 0

The semiconductor industry, the backbone of modern technology, is experiencing a rapid evolution driven by the increasing demands for higher performance, greater functionality, and lower power consumption. This evolution is creating new challenges and opportunities in the testing of mixed signal and RF semiconductors and electronics devices, making the need for adaptable and flexible test syste... » read more

Reducing Design Margins With Silicon Model Calibration
By Guy Cortez - 09 Jul, 2024 - Comments: 0

By Guy Cortez and Mark Laird It’s no secret to anyone that chip design gets harder every year. There are two major trends driving these ever-increasing challenges. The first is the continual scaling down to smaller design nodes. Although the pace of new node introduction has slowed somewhat in recent years, the impact of each new geometry and process is more dramatic than ever before. Acce... » read more

Effective Monitoring, Test, and Repair of Multi-Die Designs
By Synopsys - 09 Jul, 2024 - Comments: 0

Despite clear advantages, there are numerous new challenges that need to be addressed for successful multi-die realization. The multi-die test challenges include: Bare chiplet level (pre-bond) Probe, dedicated/functional pads for test Test, diagnosis, and repair Interconnects (mid/post-bond) Die-to-die test access Lane test, diagnosis, and repair Multi-die ... » read more

Delivering On Power During HPC Test
By Anne Meixner - 09 Jul, 2024 - Comments: 0

The industry’s insatiable need for power in high-performance computing (HPC) is creating problems for test cells, which need to deliver very high currents at very consistent voltage levels through the power delivery network (PDN). In response, ATE, wafer probe, and contactor vendors are introducing some innovative approaches and test procedures that can ensure robust power delivery to ATE pro... » read more

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