An Open Hardware Approach in Quantum Technology


A technical paper titled "Open Hardware Solutions in Quantum Technology" was published by researchers at Unitary Fund, Qruise GmbH, Technical University of Valencia, Lawrence Berkeley National Laboratory, Fermi National Accelerator Laboratory, Sandia National Laboratories, and others. Abstract "Quantum technologies such as communications, computing, and sensing offer vast opportunities for ... » read more

Cost And Quality Of Chiplets


Chiplets add a whole new challenge for the semiconductor industry. How much testing is enough? How do you optimize system binning? What’s the right amount of burn-in? The answers to these questions will vary, depending upon cost and quality tradeoffs, the number and source of the chiplets, and real-world workloads and projected lifespans. Marc Jacobs, senior director of solutions architectur... » read more

Chip Industry Technical Paper Roundup: Mar. 19


New technical papers recently added to Semiconductor Engineering’s library. [table id=206 /] More ReadingTechnical Paper Library home » read more

Research Bits: Mar. 19


Superconducting loops Researchers from University of California San Diego and University of California Riverside propose using superconducting loops to store and transmit information in a method similar to the human brain. “Our brains have this remarkable gift of associative memory, which we don't really understand,” said Robert C. Dynes, professor of physics at UC San Diego and preside... » read more

Optimizing Energy At The System Level


Power is a ubiquitous concern, and it is impossible to optimize a system's energy consumption without considering the system as a whole. Tremendous strides have been made in the optimization of a hardware implementation, but that is no longer enough. The complete system must be optimized. There are far reaching implications to this, some of which are driving the path toward domain-specific c... » read more

Predicting Warpage in Different Types of IC Stacks At Early Stage Of Package Design


A new technical paper titled "Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects" was published by researchers at Siemens EDA, D2S, and Univ. Grenoble Alpes, CEA, Leti. Abstract: "A physics-based multi-scale simulation methodology that analyses die stress variations generated by package fabrication is employed for warpage study. The ... » read more

Band-To-Band Tunneling And Negative Differential Resistance in Heterojunctions Built Entirely Using 2D Materials


A technical paper titled "Electrical characterization of multi-gated WSe2 /MoS2 van der Waals heterojunctions" was published by researchers at Helmholtz-Zentrum Dresden Rossendorf (HZDR), TU Dresden, National Institute for Materials Science (Japan) and NaMLab gGmbH. Abstract "Vertical stacking of different two-dimensional (2D) materials into van der Waals heterostructures exploits the pr... » read more

TCAM-SSD: A Framework For In-SSD Associative Search Using NAND Flash Memory


A new technical paper titled "TCAM-SSD: A Framework for Search-Based Computing in Solid-State Drives" was published by researchers at University of Illinois Urbana-Champaign, Carnegie Mellon University, Samsung Electronics and Sandia National Laboratories. Abstract "As the amount of data produced in society continues to grow at an exponential rate, modern applications are incurring signific... » read more

Environmental Impact of Semiconductor Manufacturing (ORNL)


A  technical paper titled "Cleaner Chips: Decarbonization in Semiconductor Manufacturing" was published by researchers at Oak Ridge National Laboratory (ORNL) / UT-Battelle. Abstract: "The growth of the information and communication technology sector has vastly accelerated in recent decades because of advancements in digitalization and Artificial Intelligence (AI). Scope 1, 2, and 3 gree... » read more

DRAM Chip Characterization Study of Spatial Variation of Read Disturbance and Future Solutions (ETH Zurich)


A new technical paper titled "Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions" was published by researchers at ETH Zurich. Abstract: "Read disturbance in modern DRAM chips is a widespread phenomenon and is reliably used for breaking memory isolation, a fundamental building block for building robust systems. Row... » read more

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