Powering CFETs From The Backside

By Katherine Derbyshire - 21 Mar, 2024 - Comments: 0

The first CMOS circuits to incorporate backside power connections are likely to be based on stacked nanosheet transistors, but further down the road, planners envision complementary transistors (CFETs) that vertically integrate stacked NFET and PFET devices. With at least twice the thickness of a nanosheet transistor, connecting CFETs to each other and to the rest of the circuit is likely to... » read more

Package Integrated Vapor Chamber Heat Spreaders

By Sanghyuk Kim - 21 Mar, 2024 - Comments: 0

With continuous increases in computational demand in nearly all electronics market segments, even historically lower power packaging is being driven into challenging thermal management situations. Node shrink alone is reaching a limit in maintaining track with Moore’s law. The economics and yield challenges of large monolithic system on chip (SoC) designs are driving the development of silico... » read more

The High NA EUV Imperative: How Computational Lithography Solutions Enable Us To Think Smaller

By Gandharv Bhatara - 21 Mar, 2024 - Comments: 0

The future of computing depends on miniaturization, and extreme ultraviolet lithography (EUV) is one key enabler. Until recently, we have relied on low numerical aperture (NA) EUV systems with an aperture of 0.33 to help us reduce the size of integrated circuits (ICs). As with deep ultraviolet (DUV) technology, this has begun to reach its limits. High NA EUV lithography with a 0.55 aperture rep... » read more

ESD Alliance And SEMI Efforts To Combat Design Automation Software Piracy

By Bob Smith - 21 Mar, 2024 - Comments: 0

Piracy is a growing concern for all software providers, especially those of us with complex and specialized software, such as chip design automation software that is expensive to develop and maintain. That’s why the Electronic System Design Alliance (ESD Alliance), a SEMI Technology Community, spearheaded an industry joint development effort to develop a server certification protocol that ... » read more

Rethinking Chip Economics

By Ed Sperling - 20 Mar, 2024 - Comments: 0

As process nodes shrink, so does the selection of chips developed at those nodes. Consumers demand more features and functionality, but that carries a high price tag in terms of both complexity and real dollars. In addition, because costs are skyrocketing, there is growing pressure for those chips to remain reliable and up-to-date for longer periods of time. Jayson Bethurem, vice president of m... » read more

3D-IC Intensifies Demand For Multi-Physics Simulation

By Ann Mutschler - 20 Mar, 2024 - Comments: 0

The introduction of full 3D-ICs will require a simultaneous analysis of various physical effects under different workloads, a step-function change that will add complexity at every step of the design flow, expand and alter job responsibilities, and bring together the analog and digital design worlds in unprecedented ways. 3D-ICs will be the highest-performance advanced packaging option, in s... » read more

Blog Review: March 20

By Jesse Allen - 20 Mar, 2024 - Comments: 0

Synopsys' Kiran Vittal delves into AI chips, including the expansion of chip design beyond traditional semiconductor companies, adoption of RISC-V, and the use of formal equivalence checking to verify complex AI datapaths. Siemens' Patrick McGoff points to a survey that suggests projects deploying design for manufacturing within a PCB design flow are more likely to be completed on-time, on-q... » read more

U.S. Strategy on Microelectronics Research

By Technical Paper Link - 19 Mar, 2024 - Comments: 0

The U.S. government released a 61 page report titled "National Strategy on Microelectronics Research" by the Subcommittee On Microelectronics Leadership, Committee on Homeland and National Security of the National Science and Technology Council. The report states four goals guiding the agency's efforts in microelectronics research: "Goal 1. Enable and accelerate research advances for futu... » read more

Transformer Model Based Clustering Methodology For Standard Cell Layout Automation (Nvidia)

By Technical Paper Link - 19 Mar, 2024 - Comments: 0

A new technical paper titled "Novel Transformer Model Based Clustering Method for Standard Cell Design Automation" was published by researchers at Nvidia. Abstract "Standard cells are essential components of modern digital circuit designs. With process technologies advancing beyond 5nm, more routability issues have arisen due to the decreasing number of routing tracks (RTs), increasing numb... » read more

Quantum Computing: New Ion Trap On A Microfabricated Chip (ETH Zurich)

By Technical Paper Link - 19 Mar, 2024 - Comments: 0

A new technical paper titled "Penning micro-trap for quantum computing" was published by researchers at ETH Zürich, Leibniz Universität Hannover, and Physikalisch-Technische Bundesanstalt. Abstract "Trapped ions in radio-frequency traps are among the leading approaches for realizing quantum computers, because of high-fidelity quantum gates and long coherence times. However, the use of r... » read more

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