Noise Parameter Survey Of Millimeter Wave GaN HEMT Technologies


A technical paper titled “A Survey of GaN HEMT Technologies for Millimeter-Wave Low Noise Applications” was published by researchers at Wright-Patterson AFB, Teledyne Scientific, HRL Laboratories, BAE Systems, Pseudolithic, Northrop Grumman Corporation, and University of California Santa Barbara. "This article presents a set of measured benchmarks for the noise and gain performance of si... » read more

New Type Of Hardware Trojans Based On Logic Locking


A technical paper titled “Logic Locking based Trojans: A Friend Turns Foe” was published by researchers at University of Maryland and University of Florida. Abstract: "Logic locking and hardware Trojans are two fields in hardware security that have been mostly developed independently from each other. In this paper, we identify the relationship between these two fields. We find that a com... » read more

Chip Industry’s Technical Paper Roundup: October 3


New technical papers recently added to Semiconductor Engineering’s library: [table id=150 /] Related Reading Technical Paper Library home » read more

Research Bits: October 3


Growing indium selenide at scale Researchers from the University of Pennsylvania, Brookhaven National Laboratory, and the Air Force Research Laboratory grew the 2D semiconductor indium selenide (InSe) on a full-size, industrial-scale wafer. It can also be deposited at temperatures low enough to integrate with a silicon chip. The team noted that producing large enough films of InSe has prove... » read more

Die-To-Die Security


Security concerns are growing as more chiplets or die are added into a package. There are more possible attack points, and data is becoming increasingly valuable, which makes a successful attack much more lucrative than in the past. Mike Borza, Synopsys scientist, talks about the impact of heterogeneous integration on security, what the risks are for multi-tenant data centers, and what happens ... » read more

Everyone’s A System Designer With Heterogeneous Integration


The move away from monolithic SoCs to heterogeneous chips and chiplets in a package is accelerating, setting in motion a broad shift in methodologies, collaborations, and design goals that are felt by engineers at every step of the flow, from design through manufacturing. Nearly every engineer is now working or touching some technology, process, or methodology that is new. And they are inter... » read more

Application-Optimized Processors


Executing a neural network on top of an NPU requires an understanding of application requirements, such as latency and throughput, as well as the potential partitioning challenges. Sharad Chole, chief scientist and co-founder of Expedera, talks about fine-grained dependencies, why processing packets out of order can help optimize performance and power, and when to use voltage and frequency scal... » read more

Chip Industry Week In Review


By Susan Rambo, Liz Allan, and Gregory Haley. TSMC rolled out the second version of its 3Dblox, which creates an infrastructure for stacking chiplets and other necessary components in a package, along with a standardized way of achieving that. Two novel features are chiplet mirroring for design reuse, and what is basically sandbox for power and thermal analysis of different design elements. ... » read more

LLM-Aided AI Accelerator Design Automation (Georgia Tech)


A technical paper titled “GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models” was published by researchers at Georgia Institute of Technology. Abstract: "The remarkable capabilities and intricate nature of Artificial Intelligence (AI) have dramatically escalated the imperative for specialized AI accelerators. Nonetheless, designing these accele... » read more

LLM-Assisted Generation Of Formal Verification Testbenches: RTL to SVA (Princeton)


A technical paper titled “From RTL to SVA: LLM-assisted generation of Formal Verification Testbenches” was published by researchers at Princeton University. Abstract: "Formal property verification (FPV) has existed for decades and has been shown to be effective at finding intricate RTL bugs. However, formal properties, such as those written as System Verilog Assertions (SVA), are time-con... » read more

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