Cost Characteristics of the 2.5D Chiplet-Based SiP System
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A technical paper titled "Cost-Aware Exploration for Chiplet-Based Architecture with Advanced Packaging Technologies" was published by researchers at UCSB, University of California, Santa Barbara. Abstract: "The chiplet-based System-in-Package~(SiP) technology enables more design flexibility via various inter-chiplet connection and heterogeneous integration. However, it is not known how to ... » read more

Energy of Computing As A Key Design Aspect (SLAC/Stanford, MIT)
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A technical paper titled "Trends in Energy Estimates for Computing in AI/Machine Learning Accelerators, Supercomputers, and Compute-Intensive Applications" was published by researchers at SLAC/Stanford University and MIT. Abstract: "We examine the computational energy requirements of different systems driven by the geometrical scaling law, and increasing use of Artificial Intelligence or Ma... » read more

Improving the Electrical Performance and Low-Frequency Noise Properties of p-Type TFET
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A new technical paper titled "Effect of high-pressure D2 and H2 annealing on LFN properties in FD-SOI pTFET" was published by researchers at Chungnam National University and Korea Polytechnic College. "This study investigated the effects of high-pressure deuterium (D2) annealing and hydrogen (H2) annealing on the electrical performance and low-frequency noise (LFN) of a fully depleted silic... » read more

Novel Multi-Independent Gate-Controlled FinFET Technology
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A new technical paper titled "Characteristics of a Novel FinFET with Multi-Enhanced Operation Gates (MEOG FinFET)" was published by researchers at Changzhou University. Abstract: "This study illustrates a type of novel device. Integrating fin field-effect transistors (FinFETs) with current silicon-on-insulator (SOI) wafers provides an excellent platform to fabricate advanced specific device... » read more

Red MicroLEDs Three Orders of Magnitude Smaller in Surface Area
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A technical paper titled "N-polar InGaN/GaN nanowires: overcoming the efficiency cliff of red-emitting micro-LEDs" was published by researchers at University of Michigan. The researchers created "red-microLEDs that are nearly three orders of magnitude smaller in surface area than previously reported devices while exhibiting external quantum efficiency of ~1.2%," according to the University o... » read more

Scalable Optical AI Accelerator Based on a Crossbar Architecture
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A new technical paper titled "Scalable Coherent Optical Crossbar Architecture using PCM for AI Acceleration" was published by researchers at University of Washington. Abstract: "Optical computing has been recently proposed as a new compute paradigm to meet the demands of future AI/ML workloads in datacenters and supercomputers. However, proposed implementations so far suffer from lack of sc... » read more

Using BDA To to Predict SAQP Pitch Walk
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A new technical paper titled "Bayesian dropout approximation in deep learning neural networks: analysis of self-aligned quadruple patterning" was published by researchers at IBM TJ Watson Research Center and Rensselaer Polytechnic Institute. Find the technical paper here. Published November 2022.  Open Access. Scott D. Halle, Derren N. Dunn, Allen H. Gabor, Max O. Bloomfield, and Mark Sh... » read more

Next Steps For Improving Yield
By Laura Peters - 08 Nov, 2022 - Comments: 0

Chipmakers are ramping new tools and methodologies to achieve sufficient yield faster, despite smaller device dimensions, a growing number of systematic defects, immense data volumes, and massive competitive pressure. Whether a 3nm process is ramping, or a 28nm process is being tuned, the focus is on reducing defectivity. The challenge is to rapidly identify indicators that can improve yield... » read more

Heterogeneous Integration: Correcting Overlay Errors On Advanced Integrated Circuit Substrates (AICS)
By John Chang - 08 Nov, 2022 - Comments: 0

By John Chang, with Corey Shay, James Webb, and Timothy Chang For high-performance computing, artificial intelligence, and data centers, the path ahead is certain, but with it comes a change in substrate format and processing requirements. Instead of relying on the quest for the next technology node to bring about future device performance gains, manufacturers are charting a future based inc... » read more

Legacy Tools, New Tricks: Optical 3D Inspection
By Karen Heyman - 08 Nov, 2022 - Comments: 0

Stacking chips is making it far more difficult to find existing and latent defects, and to check for things like die shift, leftover particles from other processes, co-planarity of bumps, and adhesion of different materials such as dielectrics. There are several main problems: Not everything is visible from a single angle, particularly when vertical structures are used; Various struc... » read more

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