PTAuth: Temporal Memory Safety via Robust Points-to Authentication


Authors: Reza Mirzazade Farkhani, Mansour Ahmadi, and Long Lu, Northeastern University Abstract: "Temporal memory corruptions are commonly exploited software vulnerabilities that can lead to powerful attacks. Despite significant progress made by decades of research on mitigation techniques, existing countermeasures fall short due to either limited coverage or overly high overhead. Further... » read more

Database Reconstruction from Noisy Volumes: A Cache Side-Channel Attack on SQLite


Authors: Aria Shahverdi, University of Maryland; Mahammad Shirinov, Bilkent University; Dana Dachman-Soled, University of Maryland Abstract: "We demonstrate the feasibility of database reconstruction under a cache side-channel attack on SQLite. Specifically, we present a Flush+Reload attack on SQLite that obtains approximate (or "noisy") volumes of range queries made to a private database... » read more

SMASH: Synchronized Many-sided Rowhammer Attacks from JavaScript


Authors: Finn de Ridder, ETH Zurich and VU Amsterdam; Pietro Frigo, Emanuele Vannacci, Herbert Bos, and Cristiano Giuffrida, VU Amsterdam; Kaveh Razavi, ETH Zurich Abstract: "Despite their in-DRAM Target Row Refresh (TRR) mitigations, some of the most recent DDR4 modules are still vulnerable to many-sided Rowhammer bit flips. While these bit flips are exploitable from native code, tri... » read more

Automatic Extraction of Secrets from the Transistor Jungle using Laser-Assisted Side-Channel Attacks


Abstract:  "The security of modern electronic devices relies on secret keys stored on secure hardware modules as the root-of-trust (RoT). Extracting those keys would break the security of the entire system. As shown before, sophisticated side-channel analysis (SCA) attacks, using chip failure analysis (FA) techniques, can extract data from on-chip memory cells. However, since the chip's... » read more

On the Design and Misuse of Microcoded (Embedded) Processors — A Cautionary Note


Abstract:  "Today's microprocessors often rely on microcode updates to address issues such as security or functional patches. Unfortunately, microcode update flexibility opens up new attack vectors through malicious microcode alterations. Such attacks share many features with hardware Trojans and have similar devastating consequences for system security. However, due to microcode's opaq... » read more

Usability of Authenticity Checks for Hardware Security Tokens


Abstract:  "The final responsibility to verify whether a newly purchased hardware security token (HST) is authentic and unmodified lies with the end user. However, recently reported attacks on such tokens suggest that users cannot take the security guarantees of their HSTs for granted, even despite widely deployed authenticity checks. We present the first comprehensive market review eva... » read more

Shortest Resistance Path Deception In ESD Protection Circuit P2P Debug


Verifying and fixing ESD protection circuit violations is an essential step in tapeout sign-off flows for today’s IC chip designs. As one of the most commonly used ESD verification flows, the point to point (P2P) flow checks the resistances of ESD discharge paths in layout designs to ensure they are within design thresholds. However, when debugging P2P violations, information such as the shor... » read more

Manufacturing Bits: Sept. 8


Calibrating a microphone The National Institute of Standards and Technology (NIST) has developed a faster and more accurate way to calibrate a microphone. NIST’s new calibration technique makes use of lasers, a promising technology that could supplant today’s methods. The technology could one day be used to calibrate sensitive microphones in factories, power plants and other settings li... » read more

An 8 Bit To 12 Bit Resolution Programmable 5 MSample/s Current Steering Digital-To-Analog Converter In A 22 nm FD-SOI CMOS Technology


Authors: Jeongwook Koh, Division Engineering of Adaptive Systems EAS, Fraunhofer Institute for Integrated Circuits IIS, Dresden, Germany Shishira S. Venkatesha, Dresden University of Technology, Dresden, Germany Sunil S. Rao, Division Engineering of Adaptive Systems EAS, Fraunhofer Institute for Integrated Circuits IIS, Dresden, Germany Marcel Jotschke, Division Engineering of Ad... » read more

Blog Review: Sept. 8


Synopsys' Scott Durrant considers the IP used in HPC SoCs and the efforts to simultaneously minimize data movement and maximize the speed at which data is transferred from one location to another, whether that data transfer is across long distances or from one chip to another within a server. Cadence's Paul McLellan looks into a new version of the Rowhammer DRAM vulnerability that can allow ... » read more

← Older posts Newer posts →