Edge Computing: New Support For Digital Twins
By Ansys - 08 Sep, 2021 - Comments: 0

Digital twins are one of the most exciting technology developments to emerge over the past few years. By creating a virtual model of a physical product, then simulating its real-time operation, companies are optimizing maintenance, predicting critical maintenance events and fueling innovation via actual performance feedback. Because simulation requires computational resources and the associated... » read more

Designing High-Performance Electronics For Today’s Hyperconnected Systems
By Cadence - 08 Sep, 2021 - Comments: 0

With the rapid evolution of hyperconnected devices that are managing constant and near-instantaneous data from anywhere and at any time, designing at each new technology node must overcome design and integration complexity. To do so requires automated solutions to process the scale of modern designs. Cadence system analysis solutions operate on unimaginably huge amounts of data, scaling algorit... » read more

Gallium Nitride — Gate Drive Solutions For CoolGaN 600V HEMTs
By Infineon - 08 Sep, 2021 - Comments: 0

This paper explains the gate drive requirements for Infineon’s CoolGaN 600 V e-mode HEMTs. Various driving solutions are discussed, ranging from the standard RC-coupled driver to a new differential drive concept utilizing dedicated gate driver ICs. In half-bridge topologies, a hybrid configuration combining isolated and non-isolated drivers could be an exciting alternative. Practical applicat... » read more

Functional Safety Working Group
By Accellera - 08 Sep, 2021 - Comments: 0

With the increasing demand of compute power, the electrical and electronic systems deployed in safety-critical applications become more and more complex. This complexity also extends to Functional Safety (FS) requirements, and it affects all parts of the system including hardware and software components. Addressing FS requires specific safety activities and operations, documented in what the... » read more

Power/Performance Bits: Sept. 8
By Jesse Allen - 08 Sep, 2021 - Comments: 0

Backscatter radios for 5G Researchers at the Georgia Institute of Technology, Nokia Bell Labs, and Heriot-Watt University propose using backscatter radios to support high-throughput communication and 5G-speed Gb/sec data transfer using only a single transistor. “Our breakthrough is being able to communicate over 5G/millimeter-wave (mmWave) frequencies without actually having a full mmWave... » read more

GPIOs: Critical IP For Functional Safety Applications
By Synopsys - 08 Sep, 2021 - Comments: 0

The prevalence and complexity of electronics and software (EE systems) in automotive applications are increasing with every new generation of car. The critical functions within the system on a chip (SoC) involve hardware and software that perform automotive-related signal communication at high data rates to and from the components off-chip. Every SoC includes general purpose IOs (GPIOs) on its ... » read more

In The Spotlight: What Is Responsible For The Surging Demand For CIS?
By Woo Young Han - 07 Sep, 2021 - Comments: 0

After TSMC announced plans to construct a new fab in Arizona, the Taiwan-based company disclosed that they are considering building new fabs in Japan and Germany. While the Arizona fab will focus on producing 5nm nodes using extreme ultraviolet lithography (EUV) technology, the new plant in Japan reportedly would focus on the 28nm node. This 28nm fab in Japan would be in addition to a 28nm fab ... » read more

How To Maximize Your Competitiveness In The Semiconductor Industry Using Advanced DFT
By Siemens EDA - 07 Sep, 2021 - Comments: 1

Embarking on advanced SoCs without a smart design-for-test (DFT) strategy can be harmful to your bottom line. Being competitive in today’s semiconductor market means adopting integrated, scalable, and flexible solutions to cut DFT implementation time, test costs, and time-to-market. Tessent DFT technologies, developed in partnership with industry leaders, provide the most advanced DFT and yie... » read more

The Era Of Packetized Scan Test Has Arrived
By Geir Eide - 07 Sep, 2021 - Comments: 0

For decades, process and design scaling has triggered the adoption of transformative test solutions. About twenty years ago, when at-speed test became a de-facto requirement, on-chip compression became the norm to address test data time and volume. Over the last decade, hierarchical DFT enabled DFT engineers to apply a divide and conquer on large design, improving both implementation effort and... » read more

New Memories Add New Faults
By Bryon Moyer - 07 Sep, 2021 - Comments: 1

New non-volatile memories (NVM) bring new opportunities for changing how we use memory in systems-on-chip (SoCs), but they also add new challenges for making sure they will work as expected. These new memory types – primarily MRAM and ReRAM – rely on unique physical phenomena for storing data. That means that new test sequences and fault models may be needed before they can be released t... » read more

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