Communication Algorithm-Architecture Co-Design for Distributed Deep Learning


"Abstract—Large-scale distributed deep learning training has enabled developments of more complex deep neural network models to learn from larger datasets for sophisticated tasks. In particular, distributed stochastic gradient descent intensively invokes all-reduce operations for gradient update, which dominates communication time during iterative training epochs. In this work, we identify th... » read more

Changes In Sensors And DSPs


Pulin Desai, group director for product marketing, management and business development at Cadence, talks about why processing is moving closer to the end point, how to save energy through reduced area and sensor fusion, and the impact of specialization, 3D capture and always-on circuits. » read more

Targeting Redundancy In ICs


Technology developed for one purpose is often applicable to other areas, but organizational silos can get in the way of capitalizing on it until there is a clear cost advantage. Consider memory. All memories are fabricated with spare rows and columns that are swapped in when a device fails manufacturing test. "This is a common method to increase the yield of a device, based on how much memor... » read more

Don’t Forget the I/O When Allocating Your Last-Level Cache


Source/Authors: Yifan Yuan (UIUC); Mohammad Alian (Kansas); Yipeng Wang, Ren Wang (Intel Labs); Ilia Kurakin (Intel); Charlie Tai (Intel Labs); Nam Sung Kim (UIUC) Find technical paper here. 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA.) "Abstract—In modern server CPUs, last-level cache (LLC) is a critical hardware resource that exerts significant... » read more

Ten Lessons From Three Generations Shaped Google’s TPUv4i


Source: Norman P. Jouppi, Doe Hyun Yoon, Matthew Ashcraft, Mark Gottscho, Thomas B. Jablin, George Kurian, James Laudon, Sheng Li, Peter Ma, Xiaoyu Ma, Nishant Patil, Sushma Prasad, Clifford Young, Zongwei Zhou (Google); David Patterson (Google / Berkeley) Find technical paper here. 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA) Abstract–"Google de... » read more

Week In Review: Manufacturing, Test


Chipmakers SiFive has received a takeover offer from Intel, according to a report from Bloomberg. The asking price is more than $2 billion. ------------------------------------------------------------------ IBM has filed suit against GlobalFoundries (GF), alleging fraud and breach of contract committed by GF. IBM’s suit, filed in the Supreme Court of the state of New York, seeks relief... » read more

Week In Review: Design, Low Power


Siemens Digital Industries Software acquired Pro Design's proFPGA product family of FPGA desktop prototyping technologies. Through a prior OEM relationship, proFPGA technology is already part of the Xcelerator portfolio; Siemens noted that the acquisition will allow for fuller integration with its Veloce hardware-assisted verification system. Pro Design will continue to operate as an independen... » read more

Week In Review: Auto, Security, Pervasive Computing


Pervasive computing — IoT, edge, cloud, data center, and back Xilinx introduced its Versal AI Edge series of adaptive SoCs, or adaptive compute acceleration platforms (ACAPs), that can be manage AI-ML workloads in edge applications. The chip is designed for flexible, low latency, edge applications where algorithms may need updating. The software programmable chips have an AI Engine-ML featur... » read more

Beyond The Water Cooler: 2020 Report On IC/ASIC Design And Verification Trends


Verification and design engineers like to talk shop and discuss their experiences and visions. But even though engineers sharing stories around the water cooler (whatever form that takes—conferences, blogs, etc.) does provide all kinds of valuable insights, it doesn’t provide the full picture into the very large and complicated and extremely dynamic global semiconductor industry. To better ... » read more

Getting Ready For An Efficient Shift To PCI Express 6.0 Designs With Optimized IP


PCI Express (PCIe) 6.0 technology with key changes will bring about challenges that high-performance computing, artificial intelligence, and storage system-on-chip (SoC) designers will face. This article provides designers a summary of the major changes and how they can be handled to ensure a smooth and successful transition to PCIe 6.0. The three major changes in PCIe 6.0 that designers nee... » read more

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