ISA Ownership Matters: A Tale of Three ISAs


An instruction set architecture (ISA) is crucial to the development of processors and their software ecosystems. In the last half century, the majority of ISAs have been owned by single companies, whether product companies for their own chips/systems or processor IP companies who licensed their processors to chip developers. Does ISA ownership matter? Let’s consider three proprietary ISAs a... » read more

Streaming Scan Network


The increasing complexity in large System on Chip (SoC) designs present challenges to design-for-test (DFT). Hierarchical DFT alleviates some of those challenges, by itself, is no longer enough. Adding Tessent Streaming Scan Network (SSN) technology eliminates the difficult and costly trade-offs between test implementation effort and manufacturing test cost by decoupling core-level and chip-lev... » read more

Blog Review: Jan. 27


Synopsys' Godwin Maben finds that applications like high-performance computing and AI are bringing new dynamics to the power equation, and the key power considerations for chip design that will likely emerge over the course of the year. Siemens EDA's Harry Foster checks out trends in verification technology adoption for IC and ASIC design, with increasing numbers of designs using both dynami... » read more

The Good, Bad And Unknowns Of Flexible Devices


Flexible hybrid electronics are beginning to proliferate in consumer, medical, and industrial applications due to their comparatively low weight, thin profile, and the ability to literally bend the rules of design. Open any smart phone today and you're likely to find one or more of these flexible boards. Unlike standard printed circuit boards, FHE devices are printed using a combination of r... » read more

5G NR Design eMBB


Next-generation 5G/6G communication systems will provide massive connectivity to the internet with extreme capacity, coverage, reliability, and ultra-low latency, enabling a wide range of new services made possible through innovative technologies. Enhanced mobile broadband (eMBB) extends the current mobile experience with high data throughput on the order of more than 10Gbps, high system capaci... » read more

An Automated Pre-Silicon IP Trustworthiness Assessment For Hardware Assurance


Paper presented by Sergio Marchese & John Hallman of OneSpin Solutions & The Aerospace Corporation. Integrated circuit designs include in-house and third-party intellectual properties that could contain hardware Trojans. An independent, trusted, and complete IP model, suitable for automated formal comparison with the IP register-transfer level (RTL) code using commercially available ... » read more

Manufacturing Bits: Jan. 26


EU FIB project The European Union (EU) has launched a new project to develop next-generation structures and materials using focused ion beam (FIB) systems. The EU project, dubbed Focused Ion Technology for Nanomaterials or FIT4NANO, is spearheaded by the Helmholtz-Zentrum Dresden-Rossendorf (HZDR) organization. The project aims to bring European researchers and companies together to develop... » read more

Power/Performance Bits: Jan. 26


Neural networks on MCUs Researchers at MIT are working to bring neural networks to Internet of Things devices. The team's MCUNet is a system that designs compact neural networks for deep learning on microcontrollers with limited memory and processing power. MCUNet is made up of two components. One is TinyEngine, an inference engine that directs resource management. TinyEngine is optimized t... » read more

Data Overload In The Data Center


Dealing with increasing volumes of data inside of data centers requires an understanding of architectures, the flow of data between memory and processors, bandwidth, cache coherency and new memory types and interfaces. Gary Ruggles, senior product marketing manager at Synopsys, talks about how these systems are being revamped to improve performance and reduce power. » read more

Customer-Developed, Hyper-Convergent Design Flows Are Now Possible


We all know the days of sequential, compartmentalized chip design are over. In advanced technology nodes, placement impacts performance, performance impacts power, and routing impacts everything. The way to manage these challenges is to interleave design tasks. For example, provide information on late-stage routing to early-stage synthesis tools to improve convergence. This technique is commonl... » read more

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