Smaller Nodes, Much Bigger Problems
By Ed Sperling - 15 Jul, 2020 - Comments: 3

João Geada, chief technologist at Ansys, sat down with Semiconductor Engineering to talk about device scaling, advanced packaging, increasing complexity and the growing role of AI. What follows are excerpts of that conversation. SE: We've been pushing along Moore's Law for roughly a half-century. What sorts of problems are you seeing now that you didn't see a couple nodes ago? Geada: The... » read more

Integrating FPGA: Comparison Of Chiplets Vs. eFPGA
By Geoff Tate - 15 Jul, 2020 - Comments: 0

FPGA is widely popular in systems for its flexibility and adaptability. Increasingly, it is being used in high volume applications. As volumes grow, system designers can consider integration of the FPGA into an SoC to reduce cost, reduce power and/or improve performance. There are two options for integrating FPGA into an SoC: FPGA chiplets, which replace the power hungry SERDES/PHYs wit... » read more

Why Safety-Critical Verification Is So Difficult
By Ann Mutschler - 15 Jul, 2020 - Comments: 0

The inclusion of AI chips in automotive and increasingly in avionics has put a spotlight on advanced-node designs that can meet all of the ASIL-D requirements for temperature and stress. How should designers approach this task, particularly when these devices need to last longer than the applications? Semiconductor Engineering sat down to discuss these issues with Kurt Shuler, vice president of... » read more

Vtech: Bus Performance, FPGA Debug
By Brian Bailey - 15 Jul, 2020 - Comments: 0

It has been a long time since I was able to talk about a new verification company, but today I can introduce you to Verification Technology, or Vtech for short. If you do a search for them, you will probably find a company that sells baby monitors and kids toys. This is not that company. So, let's make sure you have the right web address to start with https://vtech-usa.com/ or https://vtech-inc... » read more

Blog Review: July 15
By Jesse Allen - 15 Jul, 2020 - Comments: 0

Synopsys' Mike Borza explains DARPA's Automatic Implementation of Secure Silicon (AISS) program and why prioritizing security in the chip development and manufacturing process is so important. Mentor's Jacob Wiltgen checks out how accurate early cycle safety analysis, aided by automation, can help avoid the problem of unmet safety goals and expensive later cycle iterations. Cadence's Paul... » read more

Manufacturing Bits: July 14
By Mark LaPedus - 14 Jul, 2020 - Comments: 0

Complementary FETs At the recent 2020 Symposia on VLSI Technology and Circuits, Imec presented a paper on a 3D complementary field-effect transistor (CFET) made on 300mm wafers. As a demonstration vehicle, Imec showed a CFET based on a 14nm process. Ideally, though, CFETs are next-generation transistors that are targeted for the 1nm node in the future. On the transistor front, chipmaker... » read more

Power/Performance Bits: July 14
By Jesse Allen - 14 Jul, 2020 - Comments: 0

5G switches Researchers from the University of Texas at Austin and University of Lille built a new radio frequency switch that could save power in 5G devices when not actively jumping between different networks and spectrum frequencies. “It has become clear that the existing switches consume significant amounts of power, and that power consumed is useless power,” said Deji Akinwande, a ... » read more

It’s Eternal Spring For AI
By Rama Chellappa - 14 Jul, 2020 - Comments: 0

The field of Artificial Intelligence (AI) has had many ups and downs largely due to unrealistic expectations created by everyone involved including researchers, sponsors, developers, and even consumers. The “reemergence” of AI has lot to do with recent developments in supporting technologies and fields such as sensors, computing at macro and micro scales, communication networks and progre... » read more

Rethinking Architectures Based On Power
By Ed Sperling - 13 Jul, 2020 - Comments: 0

The newest chips being developed for everything from the cloud to the edge of the network look nothing like designs of even a year or two ago. They are architected for speed, from the throughput of high-speed buses and external interconnects to the customized accelerators and arrays of redundant MACs. But many of these designs have barely scratched the surface for saving power, which will becom... » read more

Designer And IP Tracks Swell With Focus On ML, Security And Traditional EDA Methodologies
By Michelle Clancy Fuller - 13 Jul, 2020 - Comments: 0

What are designers keenly interested in as the 57th Design Automation Conference (DAC) approaches? If you said machine learning (ML), you’d be only partially right. Based on designer and IP tracks submissions to the 57th edition of the venerable electronics-industry event, ML – how to design with it and optimize EDA tools and flows using it – is a hot topic. But so too are more traditi... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy