A Benchmark Study Of Complementary-Field Effect Transistor (CFET) Process Integration Options: Comparing Bulk vs. SOI vs. DSOI Starting Substrates


Sub-5 nm logic nodes will require an extremely high level of innovation to overcome the inherent real-estate limitations at this increased device density. One approach to increasing device density is to look at the vertical device dimension (z-direction), and stack devices on top of each other instead of conventionally side-by-side. The fabrication of a Complementary-Field Effect Transistor (CF... » read more

Blog Review: June 17


Mentor's Chris Spear provides an introduction to SystemVerilog Multidimensional Arrays and shares code samples to follow along. Cadence's Paul McLellan listens in on Sophie Wilson's 2020 Wheeler Lecture that traces the history of the microprocessor from the early days of Moore's Law through to increasing power and economic constraints that are causing a transition from general purpose to spe... » read more

SEMI 3D1 – Terminology For Through Silicon via Geometrical Metrology


Clear and commonly accepted definitions are needed for efficient communication and to prevent misunderstanding between buyers and vendors of metrology equipment and manufacturing services. The purpose of this document is to provide a consistent terminology for the understanding and discussion of metrology issues important to through silicon vias (TSV). Click here to read more, fee for access. » read more

RF And Microwave Solid-State Power Amplifiers Design Is A Speciality


In the world of RF and microwave engineering, the design and development of solid-state amplifiers is a specialty. It has always required many years of specialized engineering experience and a suitable collection of test and measurement equipment. While these will always be necessary, to be successful in the marketplace today, it is also essential to use a combination of specialized and general... » read more

Manufacturing Bits: June 16


GaN power modules Gallium-nitride (GaN) devices are emerging in several markets, such as power semiconductors and RF. GaN, a binary III-V compound, is a wide-bandgap technology, meaning it is faster and more efficient than silicon-based devices. GaN has 10 times the breakdown field strength with double the electron mobility than silicon. Generally, some GaN vendors don’t use a traditio... » read more

Simplifying And Speeding Up Verification


Semiconductor Engineering sat down to discuss what's ahead for verification with Daniel Schostak, Arm fellow and verification architect; Ty Garibay, vice president of hardware engineering at Mythic; Balachandran Rajendran, CTO at Dell EMC; Saad Godil, director of applied deep learning research at Nvidia; Nasr Ullah, senior director of performance architecture at SiFive. What follows are excerpt... » read more

Imagination’s Approach To Business In China


In my role as Imagination’s CSO, I have been asked several times today whether Imagination would hive off its China operations into a China JV. My first response to this question is “Why?” And this generates several responses.  The conversation goes something like this: “Because you have to!” No, not at all. Nobody has asked us to do that – we can transact business in China ... » read more

Power/Performance Bits: June 16


One-directional optical Researchers from University of Pennsylvania, Peking University and Massachusetts Institute of Technology developed a design for optical devices that radiate light in only one direction, which could reduce energy consumption in optical fiber networks and data centers. Light tends to flow in a single direction optical fibers, but while most of the light passing through... » read more

Interconnect Challenges Grow, Tools Lag


Interconnects are becoming much more problematic as devices shrink and the amount of data being moved around a system continues to rise. This limitation has shown up several times in the past, and it's happening again today. But when the interconnect becomes an issue, it cannot be solved in the same way issues are solved for other aspects of a chip. Typically it results in disruption in how ... » read more

How To Improve DPPM By 10X Without Affecting Yield


Chips today are under immense pressure. With wider process variation manifested at wafer and die levels in single-digit nodes, highly complex designs, and effects of application and system integration, it’s no wonder the electronics value chain is becoming ever more reliant on expensive guard-bands. The ecosystem is not yet equipped to find all existing defects during test. So while quality e... » read more

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