RF GaN Gains Steam

By Mark LaPedus - 21 Nov, 2019 - Comments: 0

Wide-bandgap semiconductors are hot topics these days. One wide-bandgap semi type--silicon carbide (SiC)--is the talk of the town and is gaining steam in electric vehicles and other systems. But let’s not forget about gallium nitride (GaN). GaN, a binary III-V material, has 10 times the breakdown field strength with double the electron mobility than silicon. GaN is used for LEDs, power ... » read more

Weighing Wafers Simplifies Metrology

By Jiangtao Hu - 21 Nov, 2019 - Comments: 2

Building semiconductors is an incredibly exacting process, with critical dimensions posing significant equipment challenges – and with the possibility that small process excursions can cause the yield to decrease. For this reason, it has always been important to measure and monitor the most critical process steps to ensure that no further processing is done on a faulty lot and so that equipme... » read more

A Study Of Next-Generation CFET Process Integration Options

By Benjamin Vincent - 21 Nov, 2019 - Comments: 0

Decision making is a critical step in semiconductor technology development. R&D semiconductor engineers must consider different design and process options early in the development of a next-generation technology. Established techniques such as Failure Mode and Effect Analysis (FMEA) can be used to select among the most promising design and process choices. Once specific design and process m... » read more

DRAM Scaling Challenges Grow

By Mark LaPedus - 21 Nov, 2019 - Comments: 5

DRAM makers are pushing into the next phase of scaling, but they are facing several challenges as the memory technology approaches its physical limit. DRAM is used for main memory in systems, and today’s most advanced devices are based on roughly 18nm to 15nm processes. The physical limit for DRAM is somewhere around 10nm. There are efforts in R&D to extend the technology, and ultimate... » read more

A Benchmark Study Of Complementary-Field Effect Transistor (CFET) Process Integration Options

By Coventor - 21 Nov, 2019 - Comments: 0

Sub-5 nm logic nodes will require an extremely high level of innovation to overcome the inherent real-estate limitations at this increased device density. One approach to increasing device density is to look at the vertical device dimension (z-direction), and stack devices on top of each other instead of conventionally side-by-side. [1] The fabrication of a Complementary-Field Effect Transistor... » read more

New Trends In Wafer Bonding

By Katherine Derbyshire - 21 Nov, 2019 - Comments: 0

Unable to scale horizontally, due to a combination of lithography delays and power constraints, manufacturers are stacking devices vertically. This has become essential as the proliferation of mobile devices drives demand for smaller circuit footprints, but the transition isn't always straightforward. Three-dimensional integration schemes take many forms, depending on the required interconne... » read more

New Developments Of Copper Plating Technology For Embedded Power Chip Packages Challenges

By ASE - 21 Nov, 2019 - Comments: 0

Copper plating has been extensively employed in the fabrication of embedded packaging to reach high-density, high-speed, high performance electronic products. With through holes (TH) as well as blind via aspect ratios increase, development of a reliable plating technology is very important. When the depth of through hole was over 200µm, it is difficult to fill without void by using direct curr... » read more

A New Playbook For The AI Era

By Ellie Yieh - 21 Nov, 2019 - Comments: 0

It’s Q4 in Silicon Valley, which means that most tech enterprises are in strategic planning mode, taking stock of where they are today and charting a course for where they want to be over the next few years. This year’s Q4 planning cycle needs to be a little different: the opportunities before us are an order of magnitude larger. So are the challenges. To get to where we need to be, our�... » read more

Planning For Panel-Level Fan-out

By Mark LaPedus - 21 Nov, 2019 - Comments: 0

Several companies are developing or ramping up panel-level fan-out packaging as a way to reduce the cost of advanced packaging. Wafer-level fan-out is one of several advanced packaging types where a package can incorporate dies, MEMS and passives in an IC package. This approach has been in production for years, and is produced in a round wafer format in 200mm or 300mm wafer sizes. Fan-out... » read more

Organ-on-Chip Systems Enable Personalized Medicine

By Serena Brischetto - 21 Nov, 2019 - Comments: 0

Healthcare has traditionally focused on one-size fits-all medication to treat populations instead of tailoring treatments to individual patients. Recent advances in stem cell technology allow researchers to create disease models for personalized medicine. SEMI spoke with Thomas Pauwelyn, Postdoctoral Researcher at imec, about trends in medical technology innovation such as organ-on-chip devices... » read more

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