Finding, Predicting EUV Stochastic Defects

By Mark LaPedus - 17 Jun, 2021 - Comments: 0

Several vendors are rolling out next-generation inspection systems and software that locates problematic defects in chips caused by processes in extreme ultraviolet (EUV) lithography. Each defect detection technology involves various tradeoffs. But it’s imperative to use one or more of them in the fab. Ultimately, these so-called stochastic-induced defects caused by EUV can impact the perf... » read more

Geopolitical And Economic Outlook For Chips And Equipment

By Ed Sperling - 17 Jun, 2021 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss geopolitical and economic changes and how they affect the chip industry with Jean-Christophe Eloy, CEO of Yole Developpement; Risto Puhakka, president of VLSI Research; Carolyn Evans, chief economist at Intel; Duncan Meldrum, chief economist at Hilltop Economics; and Rozalia Beica, head of the semiconductor business at AT&S... » read more

Using Virtual Process Libraries To Improve Semiconductor Manufacturing

By Jeonghoon (James) Kim - 17 Jun, 2021 - Comments: 0

People think that semiconductor process simulation libraries should be developed using a perfect theoretical background that is strongly supported by empirical data. This might be true in academic research, where researchers are trying to develop a systematic approach to understanding a process mechanism. However, it is definitely not true in production fabs, where engineers need to quickly a... » read more

Qualifying Exposed Pad TQFP For AEC-Q006 Grade 0

By Yoshio Matsuda - 17 Jun, 2021 - Comments: 0

Semiconductor packages used in various vehicle applications require high reliability. As technological innovations in the automotive market increase, the demand for highly reliable packaging is increasing for applications in autonomous driving, human interfaces, electric vehicles (EVs), hybrid electric vehicles (HEVs) and more. Package reliability is essential because automotive packages must p... » read more

Developing A New Curvilinear Data Format

By Jan Willis - 17 Jun, 2021 - Comments: 0

The data size generated by curvilinear masks could impact turnaround time (TAT) for photomask production and hence the adoption of curvilinear masks. In a previous blog on curvilinear masks, our panel of luminaries discuss some possible solutions in a video discussion. In this seventh video, the panel looks at some ideas to define a new curvilinear data format to reduce file sizes. Aki Fujimura... » read more

Greenfield Projects Needed To Meet Silicon Wafer Demand

By Sungho Yoon - 17 Jun, 2021 - Comments: 0

After logging record shipments in the first quarter of 2021, the silicon wafer industry may need to start greenfield projects as soon as this year to boost capacity over the next two years as market demand and average selling prices continue to improve. One segment hamstrung by a supply shortage is 300mm epitaxial wafers, a shortfall we expect to drive continuing price increases in the comin... » read more

High Thermal Die-Attach Paste Development For Analog Circuits

By Amkor - 16 Jun, 2021 - Comments: 0

In recent years, various die attach (DA) materials have been developed to cope with the higher power dissipation requirements of semiconductor devices. DA materials based on metals such as solder or sintered silver (Ag) are used for very high heat generating power devices. While they show outstanding thermal performance, the mechanical properties of these materials are less than ideal. This lim... » read more

Process Model Calibration: The Key To Building Predictive And Accurate 3D Process Models

By Coventor - 16 Jun, 2021 - Comments: 0

The semiconductor industry has always faced challenges caused by device scaling, architecture evolution, and process complexity and integration. These challenges are coupled with a need to provide new technology to the market quickly. In the initial stages of semiconductor technology development, innovative process flow schemes must be tested using silicon test wafers. These wafer tests are len... » read more

High-Temperature-Stable, Spin-On Carbon Materials For High-Aspect-Ratio Gap-Fill Applications

By Brewer Science - 16 Jun, 2021 - Comments: 0

Brewer Science, Inc. has developed a class of novel, high-temperature-stable spin-on carbon (SOC)-based materials with excellent processability. These SOCs are cured under mild conditions and have flow properties that enable the fill of high-aspect-ratio vias in a void-free manner. Moreover, this new class of SOCs has remarkable thermal stability and can survive temperatures of up to 550°C wit... » read more

Replacement Gate High-k/Metal Gate nMOSFETs Using A Self-Aligned Halo-Compensated Channel Implant

By UMC - 16 Jun, 2021 - Comments: 0

A device design technique for boosting output resistance (Rout) characteristics of long-channel halo-doped nMOSFETs for replacement gate (RMG) high-k/metal gate (HK/MG) devices is proposed based on numerical simulations. We show that the self-aligned halo-compensated channel implant (HCCI) that is carried out after dummy poly gate removal provides compensation for the conventional halo doping. ... » read more

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Knowledge Centers
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