category: Test, Measurement and Analytics

category: IoT, Security & Automotive

Advanced Outlier Die Control Technology In Fan-Out Panel Level Packaging Using Feedforward Lithography
By Onto Innovation - 12 Oct, 2021 - Comments: 0

The growing demand for heterogeneous integration is driven by the 5G market that includes smartphones, data centers, servers, HPC, AI and IoT applications. Next-generation packaging technologies require tighter overlay to accommodate a larger package size with finer pitch chip interconnects on large format flexible panels. Fan-out panel level packaging (FOPLP) is one of the technologies that... » read more

High-Speed Image Processing By GPU
By Advantest - 12 Oct, 2021 - Comments: 0

By using CPU and GPU together, we have increased the speed of the filter function that is often used in imaging tests. This feature is provided by the Image Processing Library (IPL) in T2000 CMOS Image Sensor Solution. Next IPE, our new image processing engine that is currently in development, is about six times faster than IPE3 (Image Processing Engine 3), an existing engine. Author: Chiezo... » read more

Accelerating Verification Shift Left With Intelligent Coverage Optimization
By Synopsys - 12 Oct, 2021 - Comments: 0

Functional verification dominates semiconductor development, consuming the largest percentage of project time and resources. Team members look at the rate of design bug discovery, consider anecdotal information on the types of bugs that escaped to silicon in previous projects, and use their best judgment based on their years of experience to determine when to tape out. Above all, they look at v... » read more

Growing Challenges With Wafer Bump Inspection
By Ed Sperling - 11 Oct, 2021 - Comments: 1

As advanced packaging goes mainstream, ensuring that wafer bumps are consistent has emerged as a critical concern for foundries and OSATs. John Hoffman, computer vision engineering manager at CyberOptics, talks about the shift toward middle-of-line and how that is affecting inspection and metrology, why there is so much concern over co-planarity and alignment, how variation can add up and creat... » read more

Optimizing AI Systems
By Ed Sperling - 29 Sep, 2021 - Comments: 0

Inserting AI and machine learning into chips adds a whole new dimension of complexity, and creates a variety of potential problems, including deadlocks, loss of performance, and difficulty in achieving closure on many fronts. Gajinder Panesar, fellow at Siemens EDA, talks with Semiconductor Engineering about what’s changed and how to optimize these new devices and systems by monitoring them f... » read more

SLM Is Changing The Complete Device Lifecycle Process
By Ramsay Allen - 13 Sep, 2021 - Comments: 0

Amit Sanghani, Vice President of Engineering, HW-Analytics and Test Group at Synopsys, discusses how Silicon Lifecycle Management (SLM) is changing the way we look at the complete device lifecycle process and how it can enable heightened levels of visibility in device performance, reliability and security. Learn how SLM is well placed to address the challenges that occur at every stage of cut... » read more

In The Spotlight: What Is Responsible For The Surging Demand For CIS?
By Woo Young Han - 07 Sep, 2021 - Comments: 0

After TSMC announced plans to construct a new fab in Arizona, the Taiwan-based company disclosed that they are considering building new fabs in Japan and Germany. While the Arizona fab will focus on producing 5nm nodes using extreme ultraviolet lithography (EUV) technology, the new plant in Japan reportedly would focus on the 28nm node. This 28nm fab in Japan would be in addition to a 28nm fab ... » read more

How To Maximize Your Competitiveness In The Semiconductor Industry Using Advanced DFT
By Siemens EDA - 07 Sep, 2021 - Comments: 1

Embarking on advanced SoCs without a smart design-for-test (DFT) strategy can be harmful to your bottom line. Being competitive in today’s semiconductor market means adopting integrated, scalable, and flexible solutions to cut DFT implementation time, test costs, and time-to-market. Tessent DFT technologies, developed in partnership with industry leaders, provide the most advanced DFT and yie... » read more

The Era Of Packetized Scan Test Has Arrived
By Geir Eide - 07 Sep, 2021 - Comments: 0

For decades, process and design scaling has triggered the adoption of transformative test solutions. About twenty years ago, when at-speed test became a de-facto requirement, on-chip compression became the norm to address test data time and volume. Over the last decade, hierarchical DFT enabled DFT engineers to apply a divide and conquer on large design, improving both implementation effort and... » read more

New Memories Add New Faults
By Bryon Moyer - 07 Sep, 2021 - Comments: 1

New non-volatile memories (NVM) bring new opportunities for changing how we use memory in systems-on-chip (SoCs), but they also add new challenges for making sure they will work as expected. These new memory types – primarily MRAM and ReRAM – rely on unique physical phenomena for storing data. That means that new test sequences and fault models may be needed before they can be released t... » read more

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