category: System-Level Design

category: Auto, Security & Edge AI

Challenges In Using HLS For FPGA Design
By Loren Hobbs - 29 Apr, 2019 - Comments: 0

High-level synthesis (HLS) tools, which transform C/C++ source code to Verilog/VHDL, have been commercially available for over 15 years. HLS tools from FPGA vendors and EDA companies promise improved productivity through a higher-level of abstraction, faster verification and quicker design iterations. For example, simulating your design in C/C++ can be 10 to 100x faster than simulating in RTL (... » read more

Week In Review: Design, Low Power
By Jesse Allen - 26 Apr, 2019 - Comments: 0

A new working group has been proposed by Accellera to focus on the standardization of analog/mixed signal extensions (AMS) for the Universal Verification Methodology (UVM) standard. “Our ambition is to apply UVM for both digital and analog/mixed-signal verification,” said Martin Barnasconi, Accellera Technical Committee Chair. “The UVM-AMS PWG will assess the benefits of creating analog a... » read more

Rushing To The Edge
By Ed Sperling - 25 Apr, 2019 - Comments: 0

Virtually every major tech company has an "edge" marketing presentation these days, and some even have products they are calling edge devices. But the reality is that today no one is quite sure how to define the edge or what it will become, and any attempts to pigeon-hole it are premature. What is becoming clear is the edge is not simply an extension of the Internet of Things. It is the resu... » read more

Defining Verification
By Brian Bailey - 25 Apr, 2019 - Comments: 0

There was a time when the notion of rigorous verification was seen as being unnecessary and even wasteful. I can remember early in my career working on flight control computers. We did no functional verification and created no models. We prototyped it and ran some engineering tests through it, primarily to structurally verify the system. We did not test the functionality of the system – that ... » read more

Moving Beyond Geometries: Context-Aware Verification Improves Design Quality And Reliability
By Sherif Hany - 25 Apr, 2019 - Comments: 0

Context-aware checks integrate physical and electrical information to evaluate a wide range of design conditions, from advanced design rule compliance, to circuit and reliability verification, to design optimization and finishing. Automated context-aware checking provides designers with actionable results that improve both debugging efficiency and verification precision. Introduction Many p... » read more

Hardware Trojans And The Problem Of Trust In Integrated Circuits
By Sergio Marchese - 25 Apr, 2019 - Comments: 0

Electronic systems are at the core of an ever-increasing number of products and services. From power plants to automobiles, from medical devices to airplanes, from smartphones to home appliances, complex electronic systems enable an unprecedented level of automation, performance, safety, and security. Integrated circuits (ICs) are the backbone of these systems. It is of paramount importance tha... » read more

Where Are We On The Road To Artificial Intelligence In Chip Design?
By Thomas Andersen - 25 Apr, 2019 - Comments: 0

It’s hard to find an article today that doesn’t talk about how Artificial Intelligence is going to solve every possible problem in the world. From self-driving cars, to robots running an entire hotel (in Japan), to voice assistants answering your every question, it appears that every problem can be solved with AI. As so often in life, the true answer is: it depends. It depends on the nature... » read more

Finding And Avoiding Concurrency Bugs
By Luis Murillo - 25 Apr, 2019 - Comments: 0

Understanding the intended and unintended interactions between hardware and software components is changing as architectures become more heterogeneous and interconnect topologies get more complicated. This affects performance, power consumption and cost of the project. Lots of universities are researching this from a software perspective, while a small number are looking at the implications fro... » read more

Automotive, AI Drive Big Changes In Test
By Ann Mutschler - 25 Apr, 2019 - Comments: 0

Design for test is becoming enormously more challenging at advanced nodes and in increasingly heterogeneous designs, where there may be dozens of different processing elements and memories. Historically, test was considered a necessary but rather mundane task. Much has changed over the past year or so. As systemic complexity rises, and as the role of ICs in safety-critical markets continues ... » read more

When Verification Leads
By Brian Bailey - 25 Apr, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, CEO for VTool; Adnan Hamid, CEO for Breker Verification; Mark Olen, product marketing manager for Mentor, a Siemens Business; Jim Hogan, managing partner of Vista Ventures; Sharon Rosenberg, senior solutions architect for Cadence Design Systems; and Tom... » read more

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