New Memory Options


Carlos Macián, eSilicon’s senior director of AI strategy and products, talks about how to utilize memory differently and reduce the movement of data in AI chips, and what impact that has on power and performance. https://youtu.be/wItp6wReVts » read more

The Challenge Of RISC-V Compliance


The open-source RISC-V instruction set architecture (ISA) continues to gain momentum, but the flexibility of RISC-V creates a problem—how do you know if a RISC-V implementation fits basic standards and can play well with other implementations so they all can run the same ecosystem? In addition, how do you ensure that ecosystem development works for all implementations and that all cores that ... » read more

Inaccurate Assumptions Mean Software Issues


It doesn’t seem that long ago when features and functionality were being added to next generation processors and SoCs ahead of demand. Actually, I recall when new processors were released, embedded software developers were forced to think of innovative ways to exploit the new features in order to differentiate the product to not be left behind. Today, in many respects it seems as if the... » read more

The Problem With Post-Silicon Debug


Semiconductor engineers traditionally have focused on trying to create 'perfect' GDSII at tape-out, but factors such as hardware-software interactions, increasingly heterogeneous designs, and the introduction of AI are forcing companies to rethink that approach. In the past, chipmakers typically banked on longer product cycles and multiple iterations of silicon to identify problems. This no ... » read more

The Rapid Rise Of RISC-V


The first RISC-V Summit, which took place last month in Santa Clara, CA, appears to be a watershed for the RISC-V ecosystem. The technology is maturing and the ecosystem is growing fast – and that was reflected in the nature of the presentations and news announcements we saw. The accent has started to move to how the technology will be used in real life. UltraSoC’s announcement of a har... » read more

Can Debug Be Tamed?


Debug consumes more time than any other aspect of the chip design and verification process, and it adds uncertainty and risk to semiconductor development because there are always lingering questions about whether enough bugs were caught in the allotted amount of time. Recent figures suggest that the problem is getting worse, too, as complexity and demand for reliability continue to rise. The... » read more

Reverse Debug


Chun Chan, product applications engineering director at Synopsys, talks with Semiconductor Engineering about testbench debug and how adding time markers can speed time to signoff. https://youtu.be/tx_89M1bq3Q » read more

A Conference For The Ages


The International Solid-State Circuits Conference (ISSCC) was held recently in its permanent location at the San Francisco Marriott Marquis. eSilicon had the honor of both presenting our SerDes capabilities and demonstrating the technology as well. More about that later. First, I’d like to examine the institution called ISSCC. The first ISSCC was held in 1954 in Philadelphia. Yes, 1954, that�... » read more

Optimizing Deep-Learning Inference For Embedded Devices


Deep artificial neural networks (ANNs) have emerged as universal feature extractors in various tasks as they approach (and in many cases surpass) human-level performance. They have become fundamental building blocks of almost every modern artificially intelligent (AI) application, from online shop recommendations to self-driving cars. This whitepaper highlights how different challenges relat... » read more

Smoke Testing A High-Level Synthesis Design


Designing hardware using C++ and C++ testbenches brings orders of magnitude speed-up to simulation. But after High-Level Synthesis (HLS), teams need a way to quickly ensure that the newly-generated RTL is functionally the same as the original untimed C++. They don’t want to create an RTL testbench in order to make this comparison. What teams need is an automated smoke test to quickly make the... » read more

← Older posts Newer posts →