Selective Radiation Mitigation For Integrated Circuits

By Siemens EDA - 25 Oct, 2023 - Comments: 0

Shortened lifecycles and cost reduction coupled with the demand for advanced capabilities continue to challenge project teams delivering IC into space systems. To meet these demands, project teams must continue to evolve across all aspects of the lifecycle, including the implementation and verification of mitigation protections against single event effects. This paper defines a methodology t... » read more

FIR And Median Filter Accelerators In CodAL

By Codasip - 25 Oct, 2023 - Comments: 0

5G is the latest generation of cellular networks using the 3rd Generation Partnership Project (3GPP) 5G New Radio air interface. Unlike previous generations of network (2G, 3G & 4G) which had a one-size-fits-all approach, 5G aims to address a wide range of very different applications. To flexibly support diverse quality of service requirements, network slicing is introduced to enable mul... » read more

ESD Co-Design For 224G And 112G SerDes In FinFET Technologies

By Synopsys - 25 Oct, 2023 - Comments: 0

In addressing the challenges of enhancing ESD resilience for high-speed SerDes interfaces, it's crucial to ensure the implementation of appropriate ESD protection measures. This is particularly vital during the device's lifecycle from the conclusion of silicon wafer processing to system assembly, a phase during which electronic devices are highly susceptible to Electrostatic Discharge (ESD) dam... » read more

Five Strategies To Accelerate 5G Device Development

By Keysight - 25 Oct, 2023 - Comments: 0

Designing and implementing 5G devices in new mmWave operating bands present new challenges. New technologies and evolving standards increase design complexity. Here are five strategies to help you address these challenges and get your designs to market faster. Click here to read more. » read more

Blog Review: October 25

By Jesse Allen - 25 Oct, 2023 - Comments: 0

Synopsys’ Graham Allan looks at enhancements in the LPDDR5X standard, such as a speed increase from 6.4Gbps to 8.5Gbps using the same 1.1V core voltage as LPDDR5 alongside better signal integrity, reliability, and battery efficiency. Cadence’s Krunal Patel examines the essential components and operation of MACsec, a security protocol to ensure the confidentiality and integrity of data tr... » read more

Why A DSP Is Indispensable In The New World of AI

By Cadence - 25 Oct, 2023 - Comments: 0

Chips being designed today for the automotive, mobile handset, AI-IoT (artificial intelligence - Internet of things), and other AI applications will be fabricated in a year or two, designed into end products that will hit the market in three or more years, and then have a product lifecycle of at least five years. These chips will be used in systems with a large number and various types of senso... » read more

DSP Techniques For High-Speed SerDes

By Ed Sperling - 23 Oct, 2023 - Comments: 0

Sensors everywhere, more connected devices, and the rollout of smart everything has created a flood of data. The question now is how to best handle all of that data, where to process it, and how to move it locally and to the outside network. Madhumita Sanyal, technical product manager at Synopsys, talks about the need for continuous performance improvements in SerDes, PCIe, NRZ, and PAM4, and w... » read more

Memory And High-Speed Digital Design

By Ann Mutschler - 18 Oct, 2023 - Comments: 0

As DRAM gets faster, timing constraints, jitter, and signal integrity become harder to control. The real challenge is to understand what can go wrong early in the design process, and that becomes more complex with each new version of memory and higher signal speeds. Stephen Slater, product manager for EDA products at Keysight, talks about how simulation can be applied to these issues, what to t... » read more

Why Using Commercial Chiplets Is So Difficult

By Ed Sperling - 18 Oct, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss use cases and challenges for commercial chiplets with Saif Alam, vice president of engineering at Movellus; Tony Mastroianni, advanced packaging solutions director at Siemens Digital Industries Software; Mark Kuemerle, vice president of technology at Marvell; and Craig Bishop, CTO at Deca Technologies. What follows are excerpts... » read more

Blog Review: October 18

By Jesse Allen - 18 Oct, 2023 - Comments: 0

Siemens' Stephen Chavez suggests including analog mixed signal analysis and board level parasitics within the design process from the earliest electrical design stage and throughout final release of the PCB design. Synopsys’ Filip Thoen, Leonard Drucker, and Vivek Prasad highlight how the complexities and interdependencies of multi-die systems create new challenges for software bring-up, a... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.