Are Designers’ X-Analysis Needs Different From Verification Engineers?


The propagation of unknown (X) states has become a more pressing issue with the move toward billion-gate SoC designs. Besides the sheer complexity of these designs, the common use of complex power management schemes increase the likelihood of an unknown ‘X’ state in the design translating into a functional bug in the final chip. This article describes a methodology that enables design an... » read more

Recycling Electronic Components As Fishing Lures


I have a regular search set up to help me find interesting and relevant [getkc id="16" comment="patent"] and patent applications within our industry and most of the time they are serious patents. Many come from the large EDA and semiconductor companies, systems houses and some from small startups attempting to protect their nascent technology. But one came up on my search today that was a litt... » read more

The Week In Review: System-Level Design


Si2’s OpenPDK rolled out its Open Process Specification 1.1, including elements necessary to automatically create a process design kit using any EDA vendor’s design flow. The standard uses formal grammar based on the XML Schema Definition. ARM won a deal with Rockchip, which is extending its license to a number of ARM processors as well as its GPU and interconnect technology. This marks ... » read more

Blog Review: Nov. 6


Mentor’s J VanDomelon provides some insights into a program to improve the working relationship between humans and robots, aka the Minotaur project. This is like sensitivity training for advanced weaponry. Synopsys’ Karen Bartleson rolls out part two of her discussion with Mike Malone about the phenomenon known as Silicon Valley. As with Moore’s Law, reports about impending doom, irrel... » read more

System Bits: Nov. 5


Silicon Photonics And Graphene The industry is looking towards silicon photonics that will increase the rate at which electronic systems can communicate with each other and reduce power consumption. Researchers at MIT, Columbia University and IBM’s T. J. Watson Research Center are already a few steps beyond the traditional attempts to build optical components using materials such as Gallium ... » read more

Experts At The Table: The Future Of Verification


Semiconductor Engineering sat down to discuss the future of verification with Janick Bergeron, Synopsys fellow; Harry Foster, chief verification scientist at Mentor Graphics; Frank Schirrmeister, group director of product marketing for the Cadence System Development Suite; Prakash Narain, president and CEO of Real Intent; and Yunshan Zhu, vice president of new technologies at Atrenta. What foll... » read more

The Week In Review: System-Level Design


Qualcomm bought some of Arteris’ IP assets and the bulk of its French design team, but Arteris remains a viable company with a NoC product, customers, and an infrastructure. ARM released a study, in conjunction with the Economist Intelligence Unit, that shows 75% of global business leaders are actively researching opportunities on the Internet of Things. The report says the five barriers f... » read more

Experts At The Table: Debug


Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: There are separate areas being created in devices, s... » read more

Arteris Sells Some Of Its IP Assets To Qualcomm


Qualcomm agreed to buy Arteris’ NoC technology IP and hire some of the engineers who built it, but Arteris will continue to service that IP to new and existing customers. Under terms of the agreement, the two companies also have agreed upon a roadmap for future deliverables of the IP as well as an engineering support contract. Arteris retains the source code for the FlexNoC interconnect IP pr... » read more

Blog Review: Oct. 30


Mentor’s Nazita Saye has stumbled on a phone that you can build yourself from various components. When something breaks, you simply change out what’s broken. Wasn’t that the concept behind the original Volkswagen Beetle? Cadence’s Brian Fuller launches into the discussion about 16nm headaches, including finFET parasitics, pin access and wire resistance. Looks like the transition to f... » read more

← Older posts Newer posts →