category: Top Stories

category: Auto, Security & Edge AI

Power-Delivery Network Challenges Grow
By Ed Sperling - 04 Nov, 2010 - Comments: 0

By Ann Steffora Mutschler Physics is forcing convergence in the SoC power delivery network, whose job is to ensure that every device on a chip has a robust and stable voltage so it can meet its expected functionality and timing. In the past, chip design, package design and board design were separate disciplines, guard-banded to ensure that all the parts worked well together. Today, given t... » read more

Making Software More Efficient
By Ed Sperling - 04 Nov, 2010 - Comments: 0

By Ed Sperling Software is being targeted by most of the major chip vendors and EDA companies as the next big opportunity for saving power, but exactly which software should be modified and by whom isn’t always clear. To some extent those answers depend upon which part of the software stack vendors or engineers believe can be adjusted most easily, and so far there is no widespread agreeme... » read more

Deep Dive: Energy Efficient Ethernet
By Ed Sperling - 04 Nov, 2010 - Comments: 0

By Pallab Chatterjee In late September, the IEEE ratified the 802.3az Energy Efficient Ethernet (EEE) specification. The standard, and associated test certification specification, was supported by co-development of over 20 commercial products from multiple vendors, of which 13 were release to market simultaneous with the ratification. Wael Diab, from the office of the CTO at Broadcom, and ... » read more

Redefining Performance In Mobile Devices
By Ed Sperling - 07 Oct, 2010 - Comments: 0

By Ann Steffora Mutschler While mobile product trends can be reliably unpredictable, devices are definitely moving towards supporting more software-based browsers, plug-ins for browsers, and downloaded codecs to go to browsers. This results in coming up with a best guess for performance targets. Throw power tradeoffs into the mix and things really start to get interesting. In terms of defin... » read more

User Perspective: Hardware-Software Co-Design
By Ed Sperling - 07 Oct, 2010 - Comments: 0

By Ann Steffora Mutschler With software teams today twice as large as hardware teams for any given complex SoC project, there is no doubt it is an ideal time to agree on the best way for these worlds to intersect. And even though the semiconductor industry has been actively discussing hardware-software co-design for at least a decade a mainstream solution has yet to be commercialized. Progr... » read more

Performance Plus Lower Power
By Ed Sperling - 07 Oct, 2010 - Comments: 0

By Pallab Chatterjee Power and performance often have been seen as something of a tradeoff. Chipmakers focus on one or the other, or they extract a little improvement in both at each new process node. That way of thinking is changing, though. At the recent Linley processor conference, the central theme for both standalone and embedded processors was that architectures have to optimized for ... » read more

Getting Ready For 15nm
By Ed Sperling - 07 Oct, 2010 - Comments: 0

By David Lammers The trends towards vertical transistors, non-silicon channel materials, and resistive RAMs promise to hold center stage at the 2010 IEEE International Electron Devices Meeting (IEDM), set to begin Dec. 6 in San Francisco, Calif. (www.ieee-iedm.org) Taiwan Semiconductor Manufacturing Co. (TSMC, Hsinchu, Taiwan) will present a 22/20nm technology platform based on a FinFET arc... » read more

Making Too Much Noise
By Ed Sperling - 07 Oct, 2010 - Comments: 0

By Ed Sperling For the better part of a decade talk about signal integrity in mixed-signal designs has been noticeably absent. That’s about to change. Prior to the adoption of a 130nm process, many semiconductor companies actually went on record saying they were considering abandoning plans to ever put analog and digital on the same chip because the noise on digital would interrupt signal... » read more

The Power In Errors
By Ed Sperling - 09 Sep, 2010 - Comments: 0

By David Lammers Since 1956, some of the top minds in information processing, including Claude Shannon and John von Neumann, have been pondering the problem of how to build reliable systems out of unreliable components. The communications industry embraced the challenge, and deployed error correction techniques to ensure that today’s most sensitive information is transmitted reliably over no... » read more

A New Reference For Low-Power Processors
By Ed Sperling - 09 Sep, 2010 - Comments: 0

By Pallab Chattejee Just how much power can you squeeze out of a processor without destroying performance? Ask IBM. The company introduced a new methodology for power and energy management on its multicore processor chips. The new PowerPC chip, the Power 7, has eight main processor cores each with its own L2 and L3 cache and two central memory controllers. The architecture for the design is... » read more

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