category: Top Stories

category: Auto, Security & Edge AI

Packaging’s Power Play
By Ed Sperling - 13 Jan, 2011 - Comments: 0

By Ann Steffora Mutschler In the not-too-distant past packaging was not an issue IC designers had to think much about. But now, due to smaller geometries and rising complexity, managing power in the entire system has become a major concern for system architects. IC and package designers now must work closely throughout the design process to make sure no surprises come up down the road. A... » read more

The Elusive Min Power Definition
By Ed Sperling - 10 Jan, 2011 - Comments: 0

By Ed Sperling Put a fully charged smart phone in a bad reception area and the battery will run out in a fraction of the time it normally lasts in a good reception area. While this may be an annoyance to consumers, who need to recharge their phones more often, it’s a serious problem in SoC design. Minimum power should be a simple number, but the reality is it’s more like a distribution ... » read more

The Deafening Problem Of High-Speed I/O
By Ed Sperling - 02 Dec, 2010 - Comments: 0

By Ann Steffora Mutschler The performance of digital systems today is limited by the interconnection bandwidth between chips, boards, and cabinets. This has driven I/O speeds up into the gigabytes. While this boosts performance, it also opens the door to a host of new problems within the chip, board and system. Add low-power requirements to the mix and it is a recipe for huge headaches. One... » read more

Race Intensifies To Develop EUV Source
By Ed Sperling - 02 Dec, 2010 - Comments: 0

By David Lammers The technology competition to supply the source of EUV radiation for the next-generation lithography tools has long been divided between the laser-produced plasma (LPP) approach, favored by Cymer (San Diego) and Gigaphoton (Oyama, Japan), and the discharge -produced plasma (DPP) method supported by Xtreme Technologies (Aachen, Germany). The competition is heating up, and it... » read more

3D Stacked Die Create Unique Test Issues
By Ed Sperling - 02 Dec, 2010 - Comments: 0

By Ann Steffora Mutschler While 3D die stacking promises a number of benefits including smaller footprint, faster speed, lower power and possibly lower cost, testing those devices isn’t going to be simple. There are varying degrees of challenges aligned with varying types of defects that occur throughout the process, from wafer fabrication to package assembly to system-level assembly. And... » read more

The Growing Legacy Of Moore’s Law
By Ed Sperling - 02 Dec, 2010 - Comments: 0

By Ed Sperling Moore’s Law has defined semiconductor design since it was introduced in 1965, but increasingly it also has begun defining the manufacturing equipment, the cooling needed for end devices, and both the heat and performance of systems. In the equipment sector the big problem has been the delay in rolling out extreme ultraviolet (EUV). Moore’s Law will require tighter spacing... » read more

Power Optimization Below 28nm
By Ed Sperling - 02 Dec, 2010 - Comments: 0

By Pallab Chatterjee Process scaling has normally been performed on a lithographic basis, but as processes dip below 32nm there are optimization options beyond the lithographic and area reduction. The Common Platform Group and GlobalFoundries have added the tradeoffs of power and performance optimization in addition to area in their 28nm flows. TSMC uses a five-way optimization that also h... » read more

The Trouble With Low-Power Verification
By Ed Sperling - 04 Nov, 2010 - Comments: 0

By Ed Sperling If verification accounts for 70% of the non-recurring engineering expenses in a design, what percentage does verifying a low-power design actually consume? Answer: No one knows for sure. The reason has more to do with insufficient data than tools, processes or flows. That’s also the reason that power models have never been created for more than a single design. “Power... » read more

How Software Utilizes Cores
By Ed Sperling - 04 Nov, 2010 - Comments: 2

By Ann Steffora Mutschler When writing software, how does the design engineer determine how much power it will draw on a particular targeted platform? While the question seems straightforward, the answer is not. The industry is just starting to develop the ability to get some data in that space, according to Cary Chin, director of technical marketing for Synopsys’ low-power solutions gr... » read more

Low-Power Standards Watch: Ethernet
By Ed Sperling - 04 Nov, 2010 - Comments: 0

By Colleen Taylor With a job that can legitimately count "the inherent constraints of quantum physics" as a major cause of workplace stress, engineers in the semiconductor industry have never exactly had it easy. But as policymakers focused on curbing emissions impose increasingly strict regulations on the power consumption of consumer electronic devices, a host of new challenges have emerged ... » read more

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