category: Top Stories

category: Auto, Security & Edge AI

The True Test Of IP Reuse
By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Ann Steffora Mutschler Fewer and fewer systems and semiconductor companies are designing brand new processors from scratch. Instead, they leverage as much IP as possible in their designs, investing selectivity in areas where they can add significant value. The challenges are varied from low-power issues to process technology migrations. Generally, IP consumers are doing two levels of IP-... » read more

Power Panel: IP And Other Key Issues For Future Development
By Ed Sperling - 10 Feb, 2011 - Comments: 0

Low-Power Engineering chaired a DesignCon panel of low-power experts with Bhanu Kapoor, president of Mimasic; Kesava Talupuru, DV engineer at MIPS; Prapanna Tiwari, CAE manager at Synopsys, and Rob Aitken, an ARM Fellow. What follows are excerpts of their presentations and the panel discussion that followed. Bhanu Kapoor: There are two components of power—dynamic and leakage. Dynamic is wh... » read more

Power Management Trumps Battery Technology
By Ed Sperling - 10 Feb, 2011 - Comments: 0

By Ann Steffora Mutschler The lithium-ion battery has the power to ruin someone’s day, especially when it dies and cannot be charged, not to mention occasional thermal runaways that literally cause explosions. For a technology that is about 30 years old, and approaching its limits, it is mind-boggling that the best brains on the planet haven’t come up with a technological superior alternat... » read more

Healthy Living Electronics Dominated By Power
By Ed Sperling - 10 Feb, 2011 - Comments: 0

By Pallab Chatterjee The theme for this years ISSCC (International Solid State Circuits Conference) is “Electronics for Healthy Living.” In addition to the new microprocessors, memory and data converter technologies, the focus and keynotes are directed toward health-care products. The common theme between all the talks is that health-care is being driven by mobility, information flow, a... » read more

No More Netlist Hacking
By Ed Sperling - 10 Feb, 2011 - Comments: 0

By Ann Steffora Mutschler Prior to availability of advanced physical verification tools, it was not uncommon for engineering teams to hack netlists. It sounds very clandestine, but was done out of the need to get detailed information on particular areas of the chip suspected to be a problem. Performing electrical rules checks (ERC) to improve the correctness and reliability of IC designs b... » read more

The Missing Pieces In Power Modeling—And Who’s Going To Provide Them
By Ed Sperling - 10 Feb, 2011 - Comments: 0

By Ed Sperling The push to develop power models is growing at each node, and at 22nm it will be virtually impossible to proceed without one or more models for power. Providing these kind of models is easier said than done, however. Creating an accurate power model requires accurate data from all the other pieces on a chip that potentially can affect the power. That includes how third-party ... » read more

Low Power Dominates CES
By Ed Sperling - 13 Jan, 2011 - Comments: 0

By Pallab Chatterjee The 2011 Consumer Electronics Show was dominated by tablets and other mobile devices, and the common theme was communication and data access anywhere anytime. From a design perspective, that translates into two main systems targets and one major constraint. The two targets are wireless connectivity and high performance graphics. The major constraint is power use. The power... » read more

Trouble In The Patent Office
By Ed Sperling - 13 Jan, 2011 - Comments: 0

By Ed Sperling The next wave of patents being filed in the United States involves efficiency and power rather than simply speeding up performance of chips. But the patent system is moving so slowly these days that startups are unable to talk about what exactly they do, for fear of having their IP stolen, extending the time it takes to come out of stealth mode and arrange deals with potentia... » read more

Power Model Complexity Grows
By Ed Sperling - 13 Jan, 2011 - Comments: 0

By Ed Sperling The number of factors required for an effective power model has far surpassed the capabilities of even the most detailed spreadsheet at 45nm and beyond. It has now entered the realm of complex databases and architectural tradeoffs, and those tradeoffs will become even more complex as 3D stacking takes root over the next 24 months. The idea of modeling power is hardly new, but... » read more

Material Effects: Trading Performance For Power
By Ed Sperling - 13 Jan, 2011 - Comments: 0

By Ann Steffora Mutschler Power impacts everything, even when it comes to semiconductor manufacturing materials. While bulk CMOS technology still reigns supreme, there are a number of advanced materials being suggested as replacements when it runs out of steam at around 15nm, including silicon on insulator (SOI)—particularly in combination with FinFET multigate structures on SOI—silicon ge... » read more

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