category: Top Stories

category: Auto, Security & Edge AI

Talk, Talk And More Talk
By Ed Sperling - 12 May, 2011 - Comments: 0

By Ed Sperling To anyone who owns a cell phone—and there are at least several billion people who claim that distinction these days—it’s not surprising that bad reception lowers battery life. More bars, while not the most accurate gauge of a signal, are at least an indication that you can extend the time between charges even if you’re watching streaming video. But work is under way a... » read more

ESL Power Optimization Flow Requires Ecosystem
By Ann Mutschler - 14 Apr, 2011 - Comments: 0

The issue of power optimization today is very painful for many chip architects who are tasked with determining, meeting and holding to a tight power envelope. Questions concerning how well and to what extent power can truly be understood at the architectural level, let alone optimized, are the subject of debate. The ITRS’s most recent projection provides some insight as to current market d... » read more

Power Changes Everything
By Ed Sperling - 14 Apr, 2011 - Comments: 0

By Ann Steffora Mutschler Optimizing design methodologies for effective power utilization sometimes meaning throwing out old ideas and approaches and starting fresh. This is exactly what wireless chip giant Broadcom did in its quest to manage power in its chips. Low-Power Engineering spoke with Michael Hurlston, vice president of the mobile wireless group at Broadcom, to discuss current and f... » read more

High Performance And Low Power
By Ed Sperling - 14 Apr, 2011 - Comments: 0

By Pallab Chatterjee As mobile platforms become a larger part of the component spectrum, their need for optimization beyond low power has moved to the forefront. Traditionally, standard "line-cord" based products in both the consumer and commercial sectors have used the "G" label processes from semiconductor foundries. These processes had the highest-yielding combination of design rules, d... » read more

Power Issues In 3D
By Ed Sperling - 14 Apr, 2011 - Comments: 0

By Ann Steffora Mutschler The challenges associated with implementing IP subsystems range from maintaining a consistent I/O voltage, achieving consistency in metal stacks to managing a clock distribution network and creating adequate isolation between subsystems on a chip. It’s enough to make your brain hurt. Add to that 3D or 2.5D stacking and the engineering considerations grow substantial... » read more

Rationalization For Power
By Ed Sperling - 14 Apr, 2011 - Comments: 0

By Ed Sperling Power budgets are becoming almost universally problematic. What used to be a unique headache for the cell-phone market has evolved into an ugly migraine that now includes everything with a battery—and increasingly even those devices that rely on a plug. The result is a cascade of effects that are widespread and growing. And while the drivers of this effort vary widely from ... » read more

Widening The Channels
By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Ed Sperling Wide I/O—both as a specific memory standard and as a generic approach for on-chip networking—has been looked at for the past couple of chip generations as a way of improving SoC performance. Increasingly, it also is being used as a key strategy for reducing energy consumption. Wide I/O refers to a number of different approaches in on-chip networking, ranging from through-... » read more

Power Panel: IP And Other Key Issues For Future Development
By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering chaired a DesignCon panel of low-power experts with Bhanu Kapoor, president of Mimasic; Kesava Talupuru, DV engineer at MIPS; Prapanna Tiwari, CAE manager at Synopsys, and Rob Aitken, an ARM Fellow. What follows are excerpts of their presentations and the panel discussion that followed. Prapanna Tiwari: UPF and CPF are text files that capture the power i... » read more

Gene’s Law Meets EDA
By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Pallab Chatterjee What will be the next major improvement that will cut power levels by an order of magnitude? That question was the basis of a roundtable discussion at the recent ISSC conference. Current technology provides incremental improvements each year, but the next generation of electronic systems will require dramatic changes and innovation. This premise is based on Gene’s Law... » read more

The Shocking Side Of 3D
By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Ann Steffora Mutschler The pesky static charge that builds up on your clothing when you forget the dryer sheet is more than just a nuisance when it comes to manufacturing ICs. Add 3D structures and process scaling to the mix and the challenge of adequately protecting those devices grows significantly. While this problem used to be largely an afterthought, the charged-device model type of... » read more

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