category: Top Stories

category: Auto, Security & Edge AI

Battery Progress Inches Forward
By Ed Sperling - 15 Oct, 2009 - Comments: 0

By Ed Sperling Chip companies that have been betting the future on better battery technology and holding off on the often painful process of reducing voltage should probably start rethinking their plans. Battery technology is not expected to improve by more than 3% per year, and even that may slow. Compared with the chip side, there are no breakthrough materials such as halfnium or techno... » read more

Defining Reliability In Low-Power Designs
By Ed Sperling - 15 Oct, 2009 - Comments: 0

By Ann Steffora Mutschler Having a clear understanding of what reliability means for a particular low-power application can make a significant difference when it comes to communicating with engineering team members and customers. Is reliability simply a question of how long a device can run without errors? And what happens to reliability when power modeling, verification and other design tec... » read more

Designing Systems For Power And Throughput
By Ed Sperling - 25 Sep, 2009 - Comments: 0

  By Ed Sperling The most energy being consumed inside of processors is no longer for computation. It’s stuff that’s most chip designers think about after the design is completed, such as communication inside and outside the chip, managing those communications and the power levels across the chip. Research from Intel Labs, unveiled at the Intel Developer Forum this week, show that... » read more

End User Report: The Case For Formalizing Power Modeling
By Ed Sperling - 17 Sep, 2009 - Comments: 0

While the industry clearly agrees that power modeling is a necessity for next-generation semiconductor design at the transaction level, what is lacking is a standard way to exchange power models. Low-Power Design talked with David Hathaway, Senior Technical Staff Member at IBM Electronic Design Automation and Nagu Dhanwada, Senior R&D Engineer and Team Lead for Chip Level Power Analysis T... » read more

Pulling Power Out Of Thin Air
By Ed Sperling - 17 Sep, 2009 - Comments: 0

By Cheryl Ajluni It wasn’t all that long ago that voice communication via a traditional landline was the norm. At the time, consumers would have been hard pressed to imagine a world in which anytime, anywhere communication (voice and data) with a device no bigger than the human hand was possible. Many of those same consumers might today find it hard to conceive of a world in which their... » read more

Moore’s Law vs. Low Power
By Ed Sperling - 17 Sep, 2009 - Comments: 0

By Ed Sperling Moore’s Law and low-power engineering are natural-born enemies, and this dissension is becoming more obvious at each new process node as the two forces are pushed closer together. The basic problem is that shrinking transistors and line widths between wires opens up far more real estate on a chip, which encourages chip architects and marketing chiefs at chipmakers to take... » read more

Feel The (Low) Power
By Ed Sperling - 17 Sep, 2009 - Comments: 0

By Clive (Max) Maxfield When I designed my first ASIC way back in the mists of time (circa 1980), its power consumption was the last thing on my mind. You have to remember that we're talking about a device containing only about 2,000 equivalent gates implemented in a 5 micron technology. Also, I was designing this little scamp as a gate-register-level schematic using pencil and paper (I pr... » read more

Following The WLAN Alphabet To Lower Power
By Ed Sperling - 20 Aug, 2009 - Comments: 0

By Cheryl Ajluni The quest for low power in electronic devices is one that shows no sign of abating any time soon. Pressure for it comes from many different sources, such as the continual drive to pack more functionality into ever smaller, mobile electronic devices. To try and maintain a decent battery life for today’s power-hungry “road-warriors,” engineers have to reduce power con... » read more

An Inside Look At Transaction-Level Power Modeling
By Ed Sperling - 20 Aug, 2009 - Comments: 0

By Ann Steffora Mutschler With design complexity always on the rise and an increasing amount of embedded software encapsulation in designs today, engineering teams need to be concerned with power consumption in the initial architectural design. The only way to do that is to model power consumption at the transaction level. While power is typically estimated after RTL synthesis, the better a... » read more

Mythbusters: Moore’s Law, Low Power And The Future Of Chip Design
By Ed Sperling - 20 Aug, 2009 - Comments: 0

By Ed Sperling Contrary to popular belief, Moore’s Law is not in serious trouble. Nor will active power in most devices be reduced to the millivolt or microvolt level anytime in the near future. And chip design will not disappear, be relegated to the push of a button or move offshore from one low-cost wage location to the next until ultimately it gets to a place where no one is paid a salary... » read more

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